Lines Matching +full:otp +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2005-2014, 2018-2019, 2021, 2024 Intel Corporation
9 #include "iwl-drv.h"
10 #include "iwl-debug.h"
11 #include "iwl-io.h"
12 #include "iwl-prph.h"
13 #include "iwl-csr.h"
32 #define EEPROM_LINK_HOST (2*0x64)
33 #define EEPROM_LINK_GENERAL (2*0x65)
34 #define EEPROM_LINK_REGULATORY (2*0x66)
35 #define EEPROM_LINK_CALIBRATION (2*0x67)
36 #define EEPROM_LINK_PROCESS_ADJST (2*0x68)
37 #define EEPROM_LINK_OTHERS (2*0x69)
38 #define EEPROM_LINK_TXP_LIMIT (2*0x6a)
39 #define EEPROM_LINK_TXP_LIMIT_SIZE (2*0x6b)
42 #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
43 #define EEPROM_SUBSYSTEM_ID (2*0x0A) /* 2 bytes */
44 #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
45 #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
46 #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
47 #define EEPROM_VERSION (2*0x44) /* 2 bytes */
48 #define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */
49 #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
50 #define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */
51 #define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */
61 #define EEPROM_XTAL ((2*0x128) | EEPROM_CALIB_ALL)
64 #define EEPROM_KELVIN_TEMPERATURE ((2*0x12A) | EEPROM_CALIB_ALL)
65 #define EEPROM_RAW_TEMPERATURE ((2*0x12B) | EEPROM_CALIB_ALL)
77 #define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */
78 #define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
79 #define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
80 #define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
81 #define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
82 #define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
92 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
95 static const u8 iwl_eeprom_band_2[] = { /* 4915-5080MHz */
99 static const u8 iwl_eeprom_band_3[] = { /* 5170-5320MHz */
103 static const u8 iwl_eeprom_band_4[] = { /* 5500-5700MHz */
107 static const u8 iwl_eeprom_band_5[] = { /* 5725-5825MHz */
112 1, 2, 3, 4, 5, 6, 7
128 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
130 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
146 #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
226 return -ENODATA; in iwl_eeprom_read_calib()
227 data->calib_version = hdr->version; in iwl_eeprom_read_calib()
228 data->calib_voltage = hdr->voltage; in iwl_eeprom_read_calib()
234 * enum iwl_eeprom_channel_flags - channel flags in EEPROM
252 * struct iwl_eeprom_channel - EEPROM channel data
264 IWL_EEPROM_ENH_TXP_FL_OFDM = BIT(2),
273 * struct iwl_eeprom_enhanced_txpwr - enhanced regulatory TX power limits
276 * @chain_a_max: chain a max power in 1/2 dBm
277 * @chain_b_max: chain b max power in 1/2 dBm
278 * @chain_c_max: chain c max power in 1/2 dBm
279 * @delta_20_in_40: 20-in-40 deltas (hi/lo)
280 * @mimo2_max: mimo2 max power in 1/2 dBm
281 * @mimo3_max: mimo3 max power in 1/2 dBm
303 if (data->valid_tx_ant & ANT_A && txp->chain_a_max > result) in iwl_get_max_txpwr_half_dbm()
304 result = txp->chain_a_max; in iwl_get_max_txpwr_half_dbm()
306 if (data->valid_tx_ant & ANT_B && txp->chain_b_max > result) in iwl_get_max_txpwr_half_dbm()
307 result = txp->chain_b_max; in iwl_get_max_txpwr_half_dbm()
309 if (data->valid_tx_ant & ANT_C && txp->chain_c_max > result) in iwl_get_max_txpwr_half_dbm()
310 result = txp->chain_c_max; in iwl_get_max_txpwr_half_dbm()
312 if ((data->valid_tx_ant == ANT_AB || in iwl_get_max_txpwr_half_dbm()
313 data->valid_tx_ant == ANT_BC || in iwl_get_max_txpwr_half_dbm()
314 data->valid_tx_ant == ANT_AC) && txp->mimo2_max > result) in iwl_get_max_txpwr_half_dbm()
315 result = txp->mimo2_max; in iwl_get_max_txpwr_half_dbm()
317 if (data->valid_tx_ant == ANT_ABC && txp->mimo3_max > result) in iwl_get_max_txpwr_half_dbm()
318 result = txp->mimo3_max; in iwl_get_max_txpwr_half_dbm()
328 ((txp->flags & IWL_EEPROM_ENH_TXP_FL_##x) ? # x " " : "")
338 band = txp->flags & IWL_EEPROM_ENH_TXP_FL_BAND_52G ? in iwl_eeprom_enh_txp_read_element()
342 struct ieee80211_channel *chan = &data->channels[ch_idx]; in iwl_eeprom_enh_txp_read_element()
345 if (txp->channel != 0 && chan->hw_value != txp->channel) in iwl_eeprom_enh_txp_read_element()
349 if (band != chan->band) in iwl_eeprom_enh_txp_read_element()
352 if (chan->max_power < max_txpower_avg && in iwl_eeprom_enh_txp_read_element()
353 !(txp->flags & IWL_EEPROM_ENH_TXP_FL_40MHZ)) in iwl_eeprom_enh_txp_read_element()
354 chan->max_power = max_txpower_avg; in iwl_eeprom_enh_txp_read_element()
370 /* the length is in 16-bit words, but we want entries */ in iwl_eeprom_enhanced_txpower()
373 entries = le16_to_cpup(txp_len) * 2 / EEPROM_TXP_ENTRY_LEN; in iwl_eeprom_enhanced_txpower()
381 if (!(txp->flags & IWL_EEPROM_ENH_TXP_FL_VALID)) in iwl_eeprom_enhanced_txpower()
385 (txp->channel && (txp->flags & in iwl_eeprom_enhanced_txpower()
387 "Common " : (txp->channel) ? in iwl_eeprom_enhanced_txpower()
389 (txp->channel), in iwl_eeprom_enhanced_txpower()
398 txp->flags); in iwl_eeprom_enhanced_txpower()
401 txp->chain_a_max, txp->chain_b_max, in iwl_eeprom_enhanced_txpower()
402 txp->chain_c_max); in iwl_eeprom_enhanced_txpower()
405 txp->mimo2_max, txp->mimo3_max, in iwl_eeprom_enhanced_txpower()
406 ((txp->delta_20_in_40 & 0xf0) >> 4), in iwl_eeprom_enhanced_txpower()
407 (txp->delta_20_in_40 & 0x0f)); in iwl_eeprom_enhanced_txpower()
412 DIV_ROUND_UP(max_txp_avg_halfdbm, 2)); in iwl_eeprom_enhanced_txpower()
414 if (max_txp_avg_halfdbm > data->max_tx_pwr_half_dbm) in iwl_eeprom_enhanced_txpower()
415 data->max_tx_pwr_half_dbm = max_txp_avg_halfdbm; in iwl_eeprom_enhanced_txpower()
425 u32 offset = cfg->eeprom_params->regulatory_bands[eeprom_band - 1]; in iwl_init_band_reference()
436 case 2: /* 4.9GHz band */ in iwl_init_band_reference()
468 ((eeprom_ch->flags & EEPROM_CHANNEL_##x) ? # x " " : "")
480 if (data->channels[i].band != band) in iwl_mod_ht40_chan_info()
482 if (data->channels[i].hw_value != channel) in iwl_mod_ht40_chan_info()
484 chan = &data->channels[i]; in iwl_mod_ht40_chan_info()
492 "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n", in iwl_mod_ht40_chan_info()
500 eeprom_ch->flags, in iwl_mod_ht40_chan_info()
501 eeprom_ch->max_power_avg, in iwl_mod_ht40_chan_info()
502 ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) && in iwl_mod_ht40_chan_info()
503 !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? "" in iwl_mod_ht40_chan_info()
506 if (eeprom_ch->flags & EEPROM_CHANNEL_VALID) in iwl_mod_ht40_chan_info()
507 chan->flags &= ~clear_ht40_extension_channel; in iwl_mod_ht40_chan_info()
539 if (!(eeprom_ch->flags & EEPROM_CHANNEL_VALID)) { in iwl_init_channel_map()
541 "Ch. %d Flags %x [%sGHz] - No traffic\n", in iwl_init_channel_map()
548 channel = &data->channels[n_channels]; in iwl_init_channel_map()
551 channel->hw_value = eeprom_ch_array[ch_idx]; in iwl_init_channel_map()
552 channel->band = (band == 1) ? NL80211_BAND_2GHZ in iwl_init_channel_map()
554 channel->center_freq = in iwl_init_channel_map()
556 channel->hw_value, channel->band); in iwl_init_channel_map()
558 /* set no-HT40, will enable as appropriate later */ in iwl_init_channel_map()
559 channel->flags = IEEE80211_CHAN_NO_HT40; in iwl_init_channel_map()
561 if (!(eeprom_ch->flags & EEPROM_CHANNEL_IBSS)) in iwl_init_channel_map()
562 channel->flags |= IEEE80211_CHAN_NO_IR; in iwl_init_channel_map()
564 if (!(eeprom_ch->flags & EEPROM_CHANNEL_ACTIVE)) in iwl_init_channel_map()
565 channel->flags |= IEEE80211_CHAN_NO_IR; in iwl_init_channel_map()
567 if (eeprom_ch->flags & EEPROM_CHANNEL_RADAR) in iwl_init_channel_map()
568 channel->flags |= IEEE80211_CHAN_RADAR; in iwl_init_channel_map()
570 /* Initialize regulatory-based run-time data */ in iwl_init_channel_map()
571 channel->max_power = in iwl_init_channel_map()
574 "Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n", in iwl_init_channel_map()
575 channel->hw_value, in iwl_init_channel_map()
593 if (cfg->eeprom_params->enhanced_txpower) { in iwl_init_channel_map()
606 data->max_tx_pwr_half_dbm = -128; in iwl_init_channel_map()
609 data->max_tx_pwr_half_dbm = in iwl_init_channel_map()
610 max_t(s8, data->max_tx_pwr_half_dbm, in iwl_init_channel_map()
611 data->channels[i].max_power * 2); in iwl_init_channel_map()
615 if (cfg->eeprom_params->regulatory_bands[5] == in iwl_init_channel_map()
617 cfg->eeprom_params->regulatory_bands[6] == in iwl_init_channel_map()
657 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
687 IWL_DEBUG_EEPROM(trans->dev, in iwl_eeprom_acquire_semaphore()
707 IWL_DEBUG_EEPROM(trans->dev, "EEPROM signature=0x%08x\n", gp); in iwl_eeprom_verify_signature()
714 return -ENOENT; in iwl_eeprom_verify_signature()
720 IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp); in iwl_eeprom_verify_signature()
721 return -ENOENT; in iwl_eeprom_verify_signature()
727 "bad EEPROM/OTP signature, type=%s, EEPROM_GP=0x%08x\n", in iwl_eeprom_verify_signature()
728 nvm_is_otp ? "OTP" : "EEPROM", gp); in iwl_eeprom_verify_signature()
729 return -ENOENT; in iwl_eeprom_verify_signature()
735 * OTP related functions
751 /* OTP only valid for CP/PP and after */ in iwl_nvm_is_otp()
752 switch (trans->hw_rev & CSR_HW_REV_TYPE_MSK) { in iwl_nvm_is_otp()
755 return -EIO; in iwl_nvm_is_otp()
784 * CSR auto clock gate disable bit - in iwl_init_otp_access()
785 * this is only applicable for HW with OTP shadow RAM in iwl_init_otp_access()
787 if (trans->trans_cfg->base_params->shadow_ram_support) in iwl_init_otp_access()
808 IWL_ERR(trans, "Time out reading OTP[%d]\n", addr); in iwl_read_otp_word()
816 /* set the uncorrectable OTP ECC bit for acknowledgment */ in iwl_read_otp_word()
819 IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n"); in iwl_read_otp_word()
820 return -EINVAL; in iwl_read_otp_word()
824 /* set the correctable OTP ECC bit for acknowledgment */ in iwl_read_otp_word()
827 IWL_ERR(trans, "Correctable OTP ECC error, continue read\n"); in iwl_read_otp_word()
834 * iwl_is_otp_empty: check for empty OTP
842 /* locate the beginning of OTP link list */ in iwl_is_otp_empty()
845 IWL_ERR(trans, "OTP is empty\n"); in iwl_is_otp_empty()
849 IWL_ERR(trans, "Unable to read first block of OTP list.\n"); in iwl_is_otp_empty()
858 * iwl_find_otp_image: find EEPROM image in OTP
859 * finding the OTP block that contains the EEPROM image.
862 * If all the available OTP blocks are full, the last block will be the block
876 /* checking for empty OTP or error */ in iwl_find_otp_image()
878 return -EINVAL; in iwl_find_otp_image()
882 * until reach the max number of OTP blocks in iwl_find_otp_image()
883 * different devices have different number of OTP blocks in iwl_find_otp_image()
891 IWL_DEBUG_EEPROM(trans->dev, "OTP blocks %d addr 0x%x\n", in iwl_find_otp_image()
894 return -EINVAL; in iwl_find_otp_image()
902 /* skip first 2 bytes (link list pointer) */ in iwl_find_otp_image()
903 *validblockaddr += 2; in iwl_find_otp_image()
908 } while (usedblocks <= trans->trans_cfg->base_params->max_ll_items); in iwl_find_otp_image()
910 /* OTP has no valid blocks */ in iwl_find_otp_image()
911 IWL_DEBUG_EEPROM(trans->dev, "OTP has no valid blocks\n"); in iwl_find_otp_image()
912 return -EINVAL; in iwl_find_otp_image()
916 * iwl_read_eeprom - read EEPROM contents
921 * NOTE: This routine uses the non-debug IO access functions.
935 return -EINVAL; in iwl_read_eeprom()
941 sz = trans->trans_cfg->base_params->eeprom_size; in iwl_read_eeprom()
942 IWL_DEBUG_EEPROM(trans->dev, "NVM size = %d\n", sz); in iwl_read_eeprom()
946 return -ENOMEM; in iwl_read_eeprom()
964 IWL_ERR(trans, "Failed to initialize OTP access.\n"); in iwl_read_eeprom()
976 if (!trans->trans_cfg->base_params->shadow_ram_support) { in iwl_read_eeprom()
988 e[cache_addr / 2] = eeprom_data; in iwl_read_eeprom()
1009 e[addr / 2] = cpu_to_le16(r >> 16); in iwl_read_eeprom()
1013 IWL_DEBUG_EEPROM(trans->dev, "NVM Type: %s\n", in iwl_read_eeprom()
1014 nvm_is_otp ? "OTP" : "EEPROM"); in iwl_read_eeprom()
1034 struct device *dev = trans->dev; in iwl_init_sbands()
1040 sband = &data->bands[NL80211_BAND_2GHZ]; in iwl_init_sbands()
1041 sband->band = NL80211_BAND_2GHZ; in iwl_init_sbands()
1042 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS]; in iwl_init_sbands()
1043 sband->n_bitrates = N_RATES_24; in iwl_init_sbands()
1046 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ, in iwl_init_sbands()
1047 data->valid_tx_ant, data->valid_rx_ant); in iwl_init_sbands()
1049 sband = &data->bands[NL80211_BAND_5GHZ]; in iwl_init_sbands()
1050 sband->band = NL80211_BAND_5GHZ; in iwl_init_sbands()
1051 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; in iwl_init_sbands()
1052 sband->n_bitrates = N_RATES_52; in iwl_init_sbands()
1055 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ, in iwl_init_sbands()
1056 data->valid_tx_ant, data->valid_rx_ant); in iwl_init_sbands()
1069 struct device *dev = trans->dev; in iwl_parse_eeprom_data()
1073 if (WARN_ON(!cfg || !cfg->eeprom_params)) in iwl_parse_eeprom_data()
1085 memcpy(data->hw_addr, tmp, ETH_ALEN); in iwl_parse_eeprom_data()
1086 data->n_hw_addrs = iwl_eeprom_query16(eeprom, eeprom_size, in iwl_parse_eeprom_data()
1095 memcpy(data->xtal_calib, tmp, sizeof(data->xtal_calib)); in iwl_parse_eeprom_data()
1101 data->raw_temperature = *(__le16 *)tmp; in iwl_parse_eeprom_data()
1107 data->kelvin_temperature = *(__le16 *)tmp; in iwl_parse_eeprom_data()
1108 data->kelvin_voltage = *((__le16 *)tmp + 1); in iwl_parse_eeprom_data()
1112 data->radio_cfg_dash = EEPROM_RF_CFG_DASH_MSK(radio_cfg); in iwl_parse_eeprom_data()
1113 data->radio_cfg_pnum = EEPROM_RF_CFG_PNUM_MSK(radio_cfg); in iwl_parse_eeprom_data()
1114 data->radio_cfg_step = EEPROM_RF_CFG_STEP_MSK(radio_cfg); in iwl_parse_eeprom_data()
1115 data->radio_cfg_type = EEPROM_RF_CFG_TYPE_MSK(radio_cfg); in iwl_parse_eeprom_data()
1116 data->valid_rx_ant = EEPROM_RF_CFG_RX_ANT_MSK(radio_cfg); in iwl_parse_eeprom_data()
1117 data->valid_tx_ant = EEPROM_RF_CFG_TX_ANT_MSK(radio_cfg); in iwl_parse_eeprom_data()
1121 data->sku_cap_11n_enable = sku & EEPROM_SKU_CAP_11N_ENABLE; in iwl_parse_eeprom_data()
1122 data->sku_cap_amt_enable = sku & EEPROM_SKU_CAP_AMT_ENABLE; in iwl_parse_eeprom_data()
1123 data->sku_cap_band_24ghz_enable = sku & EEPROM_SKU_CAP_BAND_24GHZ; in iwl_parse_eeprom_data()
1124 data->sku_cap_band_52ghz_enable = sku & EEPROM_SKU_CAP_BAND_52GHZ; in iwl_parse_eeprom_data()
1125 data->sku_cap_ipan_enable = sku & EEPROM_SKU_CAP_IPAN_ENABLE; in iwl_parse_eeprom_data()
1127 data->sku_cap_11n_enable = false; in iwl_parse_eeprom_data()
1129 data->nvm_version = iwl_eeprom_query16(eeprom, eeprom_size, in iwl_parse_eeprom_data()
1133 if (cfg->valid_tx_ant) in iwl_parse_eeprom_data()
1134 data->valid_tx_ant = cfg->valid_tx_ant; in iwl_parse_eeprom_data()
1135 if (cfg->valid_rx_ant) in iwl_parse_eeprom_data()
1136 data->valid_rx_ant = cfg->valid_rx_ant; in iwl_parse_eeprom_data()
1138 if (!data->valid_tx_ant || !data->valid_rx_ant) { in iwl_parse_eeprom_data()
1140 data->valid_tx_ant, data->valid_rx_ant); in iwl_parse_eeprom_data()