Lines Matching +full:0 +full:x12b
19 #define ADDRESS_MSK 0x0000FFFF
20 #define INDIRECT_TYPE_MSK 0x000F0000
21 #define INDIRECT_HOST 0x00010000
22 #define INDIRECT_GENERAL 0x00020000
23 #define INDIRECT_REGULATORY 0x00030000
24 #define INDIRECT_CALIBRATION 0x00040000
25 #define INDIRECT_PROCESS_ADJST 0x00050000
26 #define INDIRECT_OTHERS 0x00060000
27 #define INDIRECT_TXP_LIMIT 0x00070000
28 #define INDIRECT_TXP_LIMIT_SIZE 0x00080000
29 #define INDIRECT_ADDRESS 0x00100000
32 #define EEPROM_LINK_HOST (2*0x64)
33 #define EEPROM_LINK_GENERAL (2*0x65)
34 #define EEPROM_LINK_REGULATORY (2*0x66)
35 #define EEPROM_LINK_CALIBRATION (2*0x67)
36 #define EEPROM_LINK_PROCESS_ADJST (2*0x68)
37 #define EEPROM_LINK_OTHERS (2*0x69)
38 #define EEPROM_LINK_TXP_LIMIT (2*0x6a)
39 #define EEPROM_LINK_TXP_LIMIT_SIZE (2*0x6b)
42 #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
43 #define EEPROM_SUBSYSTEM_ID (2*0x0A) /* 2 bytes */
44 #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
45 #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
46 #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
47 #define EEPROM_VERSION (2*0x44) /* 2 bytes */
48 #define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */
49 #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
50 #define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */
51 #define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */
61 #define EEPROM_XTAL ((2*0x128) | EEPROM_CALIB_ALL)
64 #define EEPROM_KELVIN_TEMPERATURE ((2*0x12A) | EEPROM_CALIB_ALL)
65 #define EEPROM_RAW_TEMPERATURE ((2*0x12B) | EEPROM_CALIB_ALL)
77 #define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */
78 #define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
79 #define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
80 #define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
81 #define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
82 #define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
127 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
143 #define RATES_24_OFFS 0
153 return 0; in iwl_eeprom_query16()
160 u16 offset = 0; in eeprom_indirect_address()
162 if ((address & INDIRECT_ADDRESS) == 0) in eeprom_indirect_address()
230 return 0; in iwl_eeprom_read_calib()
243 EEPROM_CHANNEL_VALID = BIT(0),
262 IWL_EEPROM_ENH_TXP_FL_VALID = BIT(0),
300 s8 result = 0; /* (.5 dBm) */ in iwl_get_max_txpwr_half_dbm()
323 #define EEPROM_TXP_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT)
325 #define EEPROM_TXP_SZ_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT_SIZE)
341 for (ch_idx = 0; ch_idx < n_channels; ch_idx++) { in iwl_eeprom_enh_txp_read_element()
345 if (txp->channel != 0 && chan->hw_value != txp->channel) in iwl_eeprom_enh_txp_read_element()
378 for (idx = 0; idx < entries; idx++) { in iwl_eeprom_enhanced_txpower()
384 IWL_DEBUG_EEPROM(dev, "%s %d:\t %s%s%s%s%s%s%s%s (0x%02x)\n", in iwl_eeprom_enhanced_txpower()
404 "\t\t MIMO2: %d MIMO3: %d High 20_on_40: 0x%02x Low 20_on_40: 0x%02x\n", in iwl_eeprom_enhanced_txpower()
406 ((txp->delta_20_in_40 & 0xf0) >> 4), in iwl_eeprom_enhanced_txpower()
407 (txp->delta_20_in_40 & 0x0f)); in iwl_eeprom_enhanced_txpower()
461 *eeprom_ch_count = 0; in iwl_init_band_reference()
479 for (i = 0; i < n_channels; i++) { in iwl_mod_ht40_chan_info()
492 "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n", in iwl_mod_ht40_chan_info()
521 int n_channels = 0; in iwl_init_channel_map()
534 for (ch_idx = 0; ch_idx < eeprom_ch_count; ch_idx++) { in iwl_init_channel_map()
574 "Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n", in iwl_init_channel_map()
608 for (i = 0; i < n_channels; i++) in iwl_init_channel_map()
634 for (ch_idx = 0; ch_idx < eeprom_ch_count; ch_idx++) { in iwl_init_channel_map()
655 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
676 for (count = 0; count < IWL_EEPROM_SEM_RETRY_LIMIT; count++) { in iwl_eeprom_acquire_semaphore()
686 if (ret >= 0) { in iwl_eeprom_acquire_semaphore()
707 IWL_DEBUG_EEPROM(trans->dev, "EEPROM signature=0x%08x\n", gp); in iwl_eeprom_verify_signature()
712 IWL_ERR(trans, "EEPROM with bad signature: 0x%08x\n", in iwl_eeprom_verify_signature()
716 return 0; in iwl_eeprom_verify_signature()
720 IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp); in iwl_eeprom_verify_signature()
723 return 0; in iwl_eeprom_verify_signature()
727 "bad EEPROM/OTP signature, type=%s, EEPROM_GP=0x%08x\n", in iwl_eeprom_verify_signature()
760 return 0; in iwl_nvm_is_otp()
765 return 0; in iwl_nvm_is_otp()
791 return 0; in iwl_init_otp_access()
797 int ret = 0; in iwl_read_otp_word()
807 if (ret < 0) { in iwl_read_otp_word()
830 return 0; in iwl_read_otp_word()
838 u16 next_link_addr = 0; in iwl_is_otp_empty()
869 u16 next_link_addr = 0, valid_addr; in iwl_find_otp_image()
870 __le16 link_value = 0; in iwl_find_otp_image()
871 int usedblocks = 0; in iwl_find_otp_image()
891 IWL_DEBUG_EEPROM(trans->dev, "OTP blocks %d addr 0x%x\n", in iwl_find_otp_image()
904 return 0; in iwl_find_otp_image()
930 u16 validblockaddr = 0; in iwl_read_eeprom()
931 u16 cache_addr = 0; in iwl_read_eeprom()
938 if (nvm_is_otp < 0) in iwl_read_eeprom()
949 if (ret < 0) { in iwl_read_eeprom()
950 IWL_ERR(trans, "EEPROM not found, EEPROM_GP=0x%08x\n", gp); in iwl_read_eeprom()
956 if (ret < 0) { in iwl_read_eeprom()
993 for (addr = 0; addr < sz; addr += sizeof(u16)) { in iwl_read_eeprom()
1003 if (ret < 0) { in iwl_read_eeprom()
1020 return 0; in iwl_read_eeprom()
1037 int n_used = 0; in iwl_init_sbands()
1139 IWL_ERR_DEV(dev, "invalid antennas (0x%x, 0x%x)\n", in iwl_parse_eeprom_data()