Lines Matching full:l0s
4230 /* Disable L0S exit timer (platform NMI Work/Around) */ in il_apm_init()
4235 * Disable L0s without affecting L1; in il_apm_init()
4236 * don't wait for ICH L0s (ICH bug W/A) in il_apm_init()
4246 * wake device's PCI Express link L1a -> L0s in il_apm_init()
4253 * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition. in il_apm_init()
4255 * If so (likely), disable L0S, so device moves directly L0->L1; in il_apm_init()
4257 * If not (unlikely), enable L0S, so there is at least some in il_apm_init()
4263 /* L1-ASPM enabled; disable(!) L0S */ in il_apm_init()
4266 D_POWER("L1 Enabled; Disabling L0S\n"); in il_apm_init()
4268 /* L1-ASPM disabled; enable(!) L0S */ in il_apm_init()
4271 D_POWER("L1 Disabled; Enabling L0S\n"); in il_apm_init()