Lines Matching +full:0 +full:x00780000
72 #define IL_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)
73 #define IL_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16)
74 #define IL_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8)
75 #define IL_UCODE_SERIAL(ver) ((ver) & 0x000000FF)
83 N_ALIVE = 0x1,
84 N_ERROR = 0x2,
87 C_RXON = 0x10,
88 C_RXON_ASSOC = 0x11,
89 C_QOS_PARAM = 0x13,
90 C_RXON_TIMING = 0x14,
93 C_ADD_STA = 0x18,
94 C_REM_STA = 0x19,
97 C_WEPKEY = 0x20,
100 N_3945_RX = 0x1b, /* 3945 only */
101 C_TX = 0x1c,
102 C_RATE_SCALE = 0x47, /* 3945 only */
103 C_LEDS = 0x48,
104 C_TX_LINK_QUALITY_CMD = 0x4e, /* for 4965 */
107 C_CHANNEL_SWITCH = 0x72,
108 N_CHANNEL_SWITCH = 0x73,
109 C_SPECTRUM_MEASUREMENT = 0x74,
110 N_SPECTRUM_MEASUREMENT = 0x75,
113 C_POWER_TBL = 0x77,
114 N_PM_SLEEP = 0x7A,
115 N_PM_DEBUG_STATS = 0x7B,
118 C_SCAN = 0x80,
119 C_SCAN_ABORT = 0x81,
120 N_SCAN_START = 0x82,
121 N_SCAN_RESULTS = 0x83,
122 N_SCAN_COMPLETE = 0x84,
125 N_BEACON = 0x90,
126 C_TX_BEACON = 0x91,
129 C_TX_PWR_TBL = 0x97,
132 C_BT_CONFIG = 0x9b,
135 C_STATS = 0x9c,
136 N_STATS = 0x9d,
139 N_CARD_STATE = 0xa1,
142 N_MISSED_BEACONS = 0xa2,
144 C_CT_KILL_CONFIG = 0xa4,
145 C_SENSITIVITY = 0xa8,
146 C_PHY_CALIBRATION = 0xb0,
147 N_RX_PHY = 0xc0,
148 N_RX_MPDU = 0xc1,
149 N_RX = 0xc3,
150 N_COMPRESSED_BA = 0xc5,
152 IL_CN_MAX = 0xff
156 * (0)
163 #define IL_CMD_FAILED_MSK 0x40
165 #define SEQ_TO_QUEUE(s) (((s) >> 8) & 0x1f)
166 #define QUEUE_TO_SEQ(q) (((q) & 0x1f) << 8)
167 #define SEQ_TO_IDX(s) ((s) & 0xff)
168 #define IDX_TO_SEQ(i) ((i) & 0xff)
169 #define SEQ_HUGE_FRAME cpu_to_le16(0x4000)
170 #define SEQ_RX_FRAME cpu_to_le16(0x8000)
180 u8 flags; /* 0:5 reserved, 6 abort, 7 internal */
196 * 0:7 tfd idx - position within TX queue
245 * High-throughput (HT) rate format for bits 7:0 (bit 8 must be "1"):
246 * 2-0: 0) 6 Mbps
255 * 4-3: 0) Single stream (SISO)
259 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
261 * Legacy OFDM rate format for bits 7:0 (bit 8 must be "0", bit 9 "0"):
262 * 3-0: 0xD) 6 Mbps
263 * 0xF) 9 Mbps
264 * 0x5) 12 Mbps
265 * 0x7) 18 Mbps
266 * 0x9) 24 Mbps
267 * 0xB) 36 Mbps
268 * 0x1) 48 Mbps
269 * 0x3) 54 Mbps
271 * Legacy CCK rate format for bits 7:0 (bit 8 must be "0", bit 9 "1"):
272 * 6-0: 10) 1 Mbps
277 #define RATE_MCS_CODE_MSK 0x7
279 #define RATE_MCS_SPATIAL_MSK 0x18
281 #define RATE_MCS_HT_DUP_MSK 0x20
283 /* Bit 8: (1) HT format, (0) legacy format in bits 7:0 */
286 #define RATE_MCS_HT_MSK 0x100
288 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */
290 #define RATE_MCS_CCK_MSK 0x200
294 #define RATE_MCS_GF_MSK 0x400
296 /* Bit 11: (1) Use 40Mhz HT40 chnl width, (0) use 20 MHz legacy chnl width */
298 #define RATE_MCS_HT40_MSK 0x800
302 #define RATE_MCS_DUP_MSK 0x1000
304 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
306 #define RATE_MCS_SGI_MSK 0x2000
314 #define RATE_MCS_ANT_A_MSK 0x04000
315 #define RATE_MCS_ANT_B_MSK 0x08000
316 #define RATE_MCS_ANT_C_MSK 0x10000
373 * (0a)
378 #define UCODE_VALID_OK cpu_to_le32(0x1)
382 * ("Initialize") N_ALIVE = 0x1 (response only, not a command)
429 * N_ALIVE = 0x1 (response only, not a command)
446 * __le32 type; (1) timestamp with each entry, (0) no timestamp
453 * __le32 event_id; range 0 - 1500
464 * __le32 valid; (nonzero) valid, (0) log is empty
520 * N_ERROR = 0x2 (response only, not a command)
548 #define RXON_RX_CHAIN_DRIVER_FORCE_MSK cpu_to_le16(0x1 << 0)
549 #define RXON_RX_CHAIN_DRIVER_FORCE_POS (0)
550 #define RXON_RX_CHAIN_VALID_MSK cpu_to_le16(0x7 << 1)
552 #define RXON_RX_CHAIN_FORCE_SEL_MSK cpu_to_le16(0x7 << 4)
554 #define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK cpu_to_le16(0x7 << 7)
556 #define RXON_RX_CHAIN_CNT_MSK cpu_to_le16(0x3 << 10)
558 #define RXON_RX_CHAIN_MIMO_CNT_MSK cpu_to_le16(0x3 << 12)
560 #define RXON_RX_CHAIN_MIMO_FORCE_MSK cpu_to_le16(0x1 << 14)
565 #define RXON_FLG_BAND_24G_MSK cpu_to_le32(1 << 0)
576 #define RXON_FLG_ANT_SEL_MSK cpu_to_le32(0x0f00)
588 #define RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK cpu_to_le32(0x1 << 22)
592 #define RXON_FLG_HT_PROT_MSK cpu_to_le32(0x1 << 23)
593 #define RXON_FLG_HT40_PROT_MSK cpu_to_le32(0x2 << 23)
596 #define RXON_FLG_CHANNEL_MODE_MSK cpu_to_le32(0x3 << 25)
600 CHANNEL_MODE_LEGACY = 0,
613 #define RXON_FLG_SELF_CTS_EN cpu_to_le32(0x1<<30)
617 #define RXON_FILTER_PROMISC_MSK cpu_to_le32(1 << 0)
632 * C_RXON = 0x10 (command, has simple generic response)
638 * RXON_FILTER_ASSOC_MSK to 0. This will clear station-dependent
645 * issue a new C_TX_PWR_TBL after each C_RXON (0x10),
714 * C_RXON_ASSOC = 0x11 (command, has simple generic response)
740 * C_RXON_TIMING = 0x14 (command, has simple generic response)
753 * C_CHANNEL_SWITCH = 0x72 (command, has simple generic response)
776 * N_CHANNEL_SWITCH = 0x73 (notification only, not a command)
781 __le32 status; /* 0 - OK, 1 - fail */
795 * Should be a power-of-2, minus 1. Device's default is 0x0f.
797 * Should be a power-of-2, minus 1. Device's default is 0x3f.
800 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0.
815 #define QOS_PARAM_FLG_UPDATE_EDCA_MSK cpu_to_le32(0x01)
816 #define QOS_PARAM_FLG_TGN_MSK cpu_to_le32(0x02)
817 #define QOS_PARAM_FLG_TXOP_TYPE_MSK cpu_to_le32(0x10)
819 /* Number of Access Categories (AC) (EDCA), queues 0..3 */
823 * C_QOS_PARAM = 0x13 (command, has simple generic response)
826 * 0: Background, 1: Best Effort, 2: Video, 3: Voice.
843 #define IL_AP_ID 0
864 /* Use in mode field. 1: modify existing entry, 0: add new station entry */
865 #define STA_CONTROL_MODIFY_MSK 0x01
868 #define STA_KEY_FLG_ENCRYPT_MSK cpu_to_le16(0x0007)
869 #define STA_KEY_FLG_NO_ENC cpu_to_le16(0x0000)
870 #define STA_KEY_FLG_WEP cpu_to_le16(0x0001)
871 #define STA_KEY_FLG_CCMP cpu_to_le16(0x0002)
872 #define STA_KEY_FLG_TKIP cpu_to_le16(0x0003)
875 #define STA_KEY_FLG_INVALID cpu_to_le16(0x0800)
876 /* wep key is either from global key (0) or from station info array (1) */
877 #define STA_KEY_FLG_MAP_KEY_MSK cpu_to_le16(0x0008)
879 /* wep key in STA: 5-bytes (0) or 13-bytes (1) */
880 #define STA_KEY_FLG_KEY_SIZE_MSK cpu_to_le16(0x1000)
881 #define STA_KEY_MULTICAST_MSK cpu_to_le16(0x4000)
885 #define STA_MODIFY_KEY_MASK 0x01
886 #define STA_MODIFY_TID_DISABLE_TX 0x02
887 #define STA_MODIFY_TX_RATE_MSK 0x04
888 #define STA_MODIFY_ADDBA_TID_MSK 0x08
889 #define STA_MODIFY_DELBA_TID_MSK 0x10
890 #define STA_MODIFY_SLEEP_TX_COUNT_MSK 0x20
910 * @modify_mask: STA_MODIFY_*, 1: modify, 0: don't change
914 * Some idxes have special purposes (IL_AP_ID, idx 0, is for AP).
927 * C_ADD_STA = 0x18 (command)
954 u8 mode; /* 1: modify existing, 0: add new station */
961 /* bit field to disable (1) or enable (0) Tx for Traffic ID (TID)
982 u8 mode; /* 1: modify existing, 0: add new station */
989 /* bit field to disable (1) or enable (0) Tx for Traffic ID (TID)
1020 u8 mode; /* 1: modify existing, 0: add new station */
1027 /* bit field to disable (1) or enable (0) Tx for Traffic ID (TID)
1056 #define ADD_STA_SUCCESS_MSK 0x1
1057 #define ADD_STA_NO_ROOM_IN_TBL 0x2
1058 #define ADD_STA_NO_BLOCK_ACK_RESOURCE 0x4
1059 #define ADD_STA_MODIFY_NON_EXIST_STA 0x8
1061 * C_ADD_STA = 0x18 (response)
1067 #define REM_STA_SUCCESS_MSK 0x1
1069 * C_REM_STA = 0x19 (response)
1076 * C_REM_STA = 0x19 (command)
1085 #define IL_TX_FIFO_BK_MSK cpu_to_le32(BIT(0))
1089 #define IL_AGG_TX_QUEUE_MSK cpu_to_le32(0xffc00)
1091 #define IL_DROP_SINGLE 0
1096 * REPLY_WEP_KEY = 0x20
1117 #define WEP_INVALID_OFFSET 0xff
1127 #define RX_RES_STATUS_NO_CRC32_ERROR cpu_to_le32(1 << 0)
1130 #define RX_RES_PHY_FLAGS_BAND_24_MSK cpu_to_le16(1 << 0)
1134 #define RX_RES_PHY_FLAGS_ANTENNA_MSK 0x70
1138 #define RX_RES_STATUS_SEC_TYPE_MSK (0x7 << 8)
1139 #define RX_RES_STATUS_SEC_TYPE_NONE (0x0 << 8)
1140 #define RX_RES_STATUS_SEC_TYPE_WEP (0x1 << 8)
1141 #define RX_RES_STATUS_SEC_TYPE_CCMP (0x2 << 8)
1142 #define RX_RES_STATUS_SEC_TYPE_TKIP (0x3 << 8)
1143 #define RX_RES_STATUS_SEC_TYPE_ERR (0x7 << 8)
1148 #define RX_RES_STATUS_DECRYPT_TYPE_MSK (0x3 << 11)
1149 #define RX_RES_STATUS_NOT_DECRYPT (0x0 << 11)
1150 #define RX_RES_STATUS_DECRYPT_OK (0x3 << 11)
1151 #define RX_RES_STATUS_BAD_ICV_MIC (0x1 << 11)
1152 #define RX_RES_STATUS_BAD_KEY_TTAK (0x2 << 11)
1154 #define RX_MPDU_RES_STATUS_ICV_OK (0x20)
1155 #define RX_MPDU_RES_STATUS_MIC_OK (0x40)
1157 #define RX_MPDU_RES_STATUS_DEC_DONE_MSK (0x800)
1195 * N_3945_RX = 0x1b (response only, not a command)
1214 #define IL49_RX_PHY_FLAGS_ANTENNAE_MASK (0x70)
1215 #define IL49_AGC_DB_MASK (0x3f80) /* MASK(7,13) */
1219 __le16 agc_info; /* agc code 0:6, agc dB 7:13, reserved 14:15 */
1220 u8 rssi_info[6]; /* we use even entries, 0/2/4 for A/B/C rssi */
1225 * N_RX = 0xc3 (response only, not a command)
1289 * 0: Don't expect ACK (MAC header's duration field s/b 0)
1297 * 0: Use Tx rate/MCS from Tx command's rate_n_flags field.
1311 /* Tx antenna selection field; used only for 3945, reserved (0) for 4965 devices.
1312 * Set field to "0" to allow 3945 uCode to select antenna (normal usage). */
1313 #define TX_CMD_FLG_ANT_SEL_MSK cpu_to_le32(0xf00)
1318 * 0: Driver provides sequence control field in MAC header.
1324 * 0: Last fragment, or not using fragmentation. */
1328 * 0: No TSF required in outgoing frame.
1334 * 0: No pad
1341 * 0 - no CCMP encryption; 1 - CCMP encryption */
1350 #define TX_CMD_SEC_WEP 0x01
1351 #define TX_CMD_SEC_CCM 0x02
1352 #define TX_CMD_SEC_TKIP 0x03
1353 #define TX_CMD_SEC_MSK 0x03
1355 #define TX_CMD_SEC_KEY128 0x08
1358 * C_TX = 0x1c (command)
1379 * Same as "len", but for next frame. Set to 0 if not applicable.
1427 * C_TX = 0x1c (response)
1441 * Driver should set these fields to 0.
1467 * Same as "len", but for next frame. Set to 0 if not applicable.
1488 * Tx attempt, if TX_CMD_FLG_STA_RATE_MSK is set. Normally "0" for
1490 * rate (via non-0 value) for special frames (e.g. management), while
1504 * Must be dword aligned. "0" in dram_lsb_ptr disables usage. */
1560 TX_3945_STATUS_SUCCESS = 0x01,
1561 TX_3945_STATUS_DIRECT_DONE = 0x02,
1562 TX_3945_STATUS_FAIL_SHORT_LIMIT = 0x82,
1563 TX_3945_STATUS_FAIL_LONG_LIMIT = 0x83,
1564 TX_3945_STATUS_FAIL_FIFO_UNDERRUN = 0x84,
1565 TX_3945_STATUS_FAIL_MGMNT_ABORT = 0x85,
1566 TX_3945_STATUS_FAIL_NEXT_FRAG = 0x86,
1567 TX_3945_STATUS_FAIL_LIFE_EXPIRE = 0x87,
1568 TX_3945_STATUS_FAIL_DEST_PS = 0x88,
1569 TX_3945_STATUS_FAIL_ABORTED = 0x89,
1570 TX_3945_STATUS_FAIL_BT_RETRY = 0x8a,
1571 TX_3945_STATUS_FAIL_STA_INVALID = 0x8b,
1572 TX_3945_STATUS_FAIL_FRAG_DROPPED = 0x8c,
1573 TX_3945_STATUS_FAIL_TID_DISABLE = 0x8d,
1574 TX_3945_STATUS_FAIL_FRAME_FLUSHED = 0x8e,
1575 TX_3945_STATUS_FAIL_INSUFFICIENT_CF_POLL = 0x8f,
1576 TX_3945_STATUS_FAIL_TX_LOCKED = 0x90,
1577 TX_3945_STATUS_FAIL_NO_BEACON_ON_RADAR = 0x91,
1588 TX_STATUS_SUCCESS = 0x01,
1589 TX_STATUS_DIRECT_DONE = 0x02,
1591 TX_STATUS_POSTPONE_DELAY = 0x40,
1592 TX_STATUS_POSTPONE_FEW_BYTES = 0x41,
1593 TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43,
1594 TX_STATUS_POSTPONE_CALC_TTAK = 0x44,
1596 TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81,
1597 TX_STATUS_FAIL_SHORT_LIMIT = 0x82,
1598 TX_STATUS_FAIL_LONG_LIMIT = 0x83,
1599 TX_STATUS_FAIL_FIFO_UNDERRUN = 0x84,
1600 TX_STATUS_FAIL_DRAIN_FLOW = 0x85,
1601 TX_STATUS_FAIL_RFKILL_FLUSH = 0x86,
1602 TX_STATUS_FAIL_LIFE_EXPIRE = 0x87,
1603 TX_STATUS_FAIL_DEST_PS = 0x88,
1604 TX_STATUS_FAIL_HOST_ABORTED = 0x89,
1605 TX_STATUS_FAIL_BT_RETRY = 0x8a,
1606 TX_STATUS_FAIL_STA_INVALID = 0x8b,
1607 TX_STATUS_FAIL_FRAG_DROPPED = 0x8c,
1608 TX_STATUS_FAIL_TID_DISABLE = 0x8d,
1609 TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e,
1610 TX_STATUS_FAIL_INSUFFICIENT_CF_POLL = 0x8f,
1611 TX_STATUS_FAIL_PASSIVE_NO_RX = 0x90,
1612 TX_STATUS_FAIL_NO_BEACON_ON_RADAR = 0x91,
1615 #define TX_PACKET_MODE_REGULAR 0x0000
1616 #define TX_PACKET_MODE_BURST_SEQ 0x0100
1617 #define TX_PACKET_MODE_BURST_FIRST 0x0200
1620 TX_POWER_PA_NOT_ACTIVE = 0x0,
1624 TX_STATUS_MSK = 0x000000ff, /* bits 0:7 */
1625 TX_STATUS_DELAY_MSK = 0x00000040,
1626 TX_STATUS_ABORT_MSK = 0x00000080,
1627 TX_PACKET_MODE_MSK = 0x0000ff00, /* bits 8:15 */
1628 TX_FIFO_NUMBER_MSK = 0x00070000, /* bits 16:18 */
1629 TX_RESERVED = 0x00780000, /* bits 19:22 */
1630 TX_POWER_PA_DETECT_MSK = 0x7f800000, /* bits 23:30 */
1631 TX_ABORT_REQUIRED_MSK = 0x80000000, /* bits 31:31 */
1639 AGG_TX_STATE_TRANSMITTED = 0x00,
1640 AGG_TX_STATE_UNDERRUN_MSK = 0x01,
1641 AGG_TX_STATE_FEW_BYTES_MSK = 0x04,
1642 AGG_TX_STATE_ABORT_MSK = 0x08,
1643 AGG_TX_STATE_LAST_SENT_TTL_MSK = 0x10,
1644 AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK = 0x20,
1645 AGG_TX_STATE_SCD_QUERY_MSK = 0x80,
1646 AGG_TX_STATE_TEST_BAD_CRC32_MSK = 0x100,
1647 AGG_TX_STATE_RESPONSE_MSK = 0x1ff,
1648 AGG_TX_STATE_DUMP_TX_MSK = 0x200,
1649 AGG_TX_STATE_DELAY_TX_MSK = 0x400
1652 #define AGG_TX_STATUS_MSK 0x00000fff /* bits 0:11 */
1653 #define AGG_TX_TRY_MSK 0x0000f000 /* bits 12:15 */
1660 #define AGG_TX_STATE_TRY_CNT_MSK 0xf000
1664 #define AGG_TX_STATE_SEQ_NUM_MSK 0xffff0000
1667 * C_TX = 0x1c (response)
1716 * 11- 0: AGG_TX_STATE_* status code
1731 * N_COMPRESSED_BA = 0xc5 (response only, not a command)
1750 * C_TX_PWR_TBL = 0x97 (command, has simple generic response)
1756 u8 band; /* 0: 5 GHz, 1: 2.4 GHz */
1763 u8 band; /* 0: 5 GHz, 1: 2.4 GHz */
1772 * C_RATE_SCALE = 0x47 (command, has simple generic response)
1779 * For example, if you set 9MB (PLCP 0x0f) as the first
1782 * command would be bit 0 (1 << 0)
1796 /*RS_NEW_API: only TLC_RTS remains and moved to bit 0 */
1797 #define LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK (1 << 0)
1806 #define LINK_QUAL_ANT_A_MSK (1 << 0)
1829 * EDCA QOS access categories (as implemented by tx fifos 0-3),
1832 * Otherwise, driver should set all entries to 0.
1835 * 0 = Background, 1 = Best Effort (normal), 2 = Video, 3 = Voice
1836 * TX FIFOs above 3 use same value (typically 0) as TX FIFO 3.
1847 #define LINK_QUAL_AGG_DISABLE_START_MIN (0)
1851 #define LINK_QUAL_AGG_FRAME_LIMIT_MIN (0)
1876 * 0 = no limit (default). 1 = no aggregation.
1885 * C_TX_LINK_QUALITY_CMD = 0x4e (command, has simple generic response)
1942 * includes a shifting bitmap of success(1)/failure(0), and sums of successful
2050 * A: 0 0 0 0 40 57 72 98 121 154 177 186 186
2051 * SISO 20MHz: 0 0 0 0 42 42 76 102 124 159 183 193 202
2052 * SGI SISO 20MHz: 0 0 0 0 46 46 82 110 132 168 192 202 211
2053 * MIMO 20MHz: 0 0 0 0 74 74 123 155 179 214 236 244 251
2054 * SGI MIMO 20MHz: 0 0 0 0 81 81 131 164 188 222 243 251 257
2055 * SISO 40MHz: 0 0 0 0 77 77 127 160 184 220 242 250 257
2056 * SGI SISO 40MHz: 0 0 0 0 83 83 135 169 193 229 250 257 264
2057 * MIMO 40MHz: 0 0 0 0 123 123 182 214 235 264 279 285 289
2058 * SGI MIMO 40MHz: 0 0 0 0 131 131 191 222 242 270 284 289 293
2094 * bit 0 - 1: BT channel announcement enabled
2095 * 0: disable
2097 * 0: disable
2099 #define BT_COEX_DISABLE (0x0)
2100 #define BT_ENABLE_CHANNEL_ANNOUNCE BIT(0)
2105 #define BT_LEAD_TIME_DEF (0x1E)
2107 #define BT_MAX_KILL_DEF (0x5)
2110 * C_BT_CONFIG = 0x9b (command, has simple generic response)
2151 * C_SPECTRUM_MEASUREMENT = 0x74 (command)
2156 u8 id; /* measurement id -- 0 or 1 */
2157 u8 origin; /* 0 = TGh, 1 = other, 2 = TGk */
2170 * C_SPECTRUM_MEASUREMENT = 0x74 (response)
2174 u8 id; /* id of the prior command replaced, or 0xff */
2175 __le16 status; /* 0 - command will be handled
2181 IL_MEASUREMENT_START = 0,
2186 IL_MEASUREMENT_OK = 0,
2210 IL_MEASURE_BASIC = (1 << 0),
2220 * N_SPECTRUM_MEASUREMENT = 0x75 (notification only, not a command)
2223 u8 id; /* measurement id -- 0 or 1 */
2226 u8 state; /* 0 - start, 1 - stop */
2228 u8 band; /* 0 - 5.2GHz, 1 - 2.4GHz */
2237 u8 basic_type; /* 0 - bss, 1 - ofdm preamble, 2 -
2255 * C_POWER_TBL = 0x77 (command, has simple generic response)
2258 * bit 0 - '0' Driver not allow power management
2262 * bit 1 - '0' Don't send sleep notification
2266 * bit 2 - '0' PM have to walk up every DTIM
2270 * bit 3 - '0' (PCI_CFG_LINK_CTRL & 0x1)
2271 * '1' !(PCI_CFG_LINK_CTRL & 0x1)
2288 #define IL_POWER_DRIVER_ALLOW_SLEEP_MSK cpu_to_le16(BIT(0))
2311 * N_PM_SLEEP = 0x7A (notification only, not a command)
2325 IL_PM_NO_SLEEP = 0,
2339 * N_CARD_STATE = 0xa1 (notification only, not a command)
2345 #define HW_CARD_DISABLED 0x01
2346 #define SW_CARD_DISABLED 0x02
2347 #define CT_CARD_DISABLED 0x04
2348 #define RXON_CARD_DISABLED 0x10
2362 #define SCAN_CHANNEL_TYPE_PASSIVE cpu_to_le32(0)
2377 * 1) If using passive_dwell (i.e. passive_dwell != 0):
2378 * active_dwell <= passive_dwell (< max_out_time if max_out_time != 0)
2380 * 3) If restricting off-channel time (i.e. max_out_time !=0):
2387 * 0:0 1 = active, 0 = passive
2405 * 0:0 1 = active, 0 = passive
2437 #define TX_CMD_LIFE_TIME_INFINITE cpu_to_le32(0xFFFFFFFF)
2438 #define IL_GOOD_CRC_TH_DISABLED 0
2440 #define IL_GOOD_CRC_TH_NEVER cpu_to_le16(0xffff)
2445 * C_SCAN = 0x80 (command)
2474 * 9) Sends NULL packet with PS=0 to tell AP that we're back
2510 * 3945; 31:24 # beacons, 19:0 additional usec,
2511 * 4965; 31:22 # beacons, 21:0 additional usec.
2516 /* For active scans (set to all-0s for passive scans).
2520 /* For directed active scans (set to all-0s otherwise) */
2531 * struct il3945_scan_channel channels[0];
2554 * 3945; 31:24 # beacons, 19:0 additional usec,
2555 * 4965; 31:22 # beacons, 21:0 additional usec.
2560 /* For active scans (set to all-0s for passive scans).
2564 /* For directed active scans (set to all-0s otherwise) */
2575 * struct il_scan_channel channels[0];
2586 #define CAN_ABORT_STATUS cpu_to_le32(0x1)
2588 #define ABORT_STATUS 0x2
2591 * C_SCAN = 0x80 (response)
2598 * N_SCAN_START = 0x82 (notification only, not a command)
2610 #define SCAN_OWNER_STATUS 0x1
2611 #define MEASURE_OWNER_STATUS 0x2
2613 #define IL_PROBE_STATUS_OK 0
2614 #define IL_PROBE_STATUS_TX_FAILED BIT(0)
2621 * N_SCAN_RESULTS = 0x83 (notification only, not a command)
2634 * N_SCAN_COMPLETE = 0x84 (notification only, not a command)
2651 IL_NOT_IBSS_MANAGER = 0,
2656 * N_BEACON = 0x90 (notification only, not a command)
2674 * C_TX_BEACON= 0x91 (command, has simple generic response)
2949 #define UCODE_STATS_CLEAR_MSK (0x1 << 0)
2950 #define UCODE_STATS_FREQUENCY_MSK (0x1 << 1)
2951 #define UCODE_STATS_NARROW_BAND_MSK (0x1 << 2)
2954 * C_STATS = 0x9c,
2958 * The response is in the same format as N_STATS 0x9d, below.
2966 * does not affect the response to the C_STATS 0x9c itself.
2968 #define IL_STATS_CONF_CLEAR_STATS cpu_to_le32(0x1) /* see above */
2969 #define IL_STATS_CONF_DISABLE_NOTIF cpu_to_le32(0x2) /* see above */
2975 * N_STATS = 0x9d (notification only, not a command)
2979 * C_STATS 0x9c, above.
2983 * 0x9c with CLEAR_STATS bit set (see above).
2989 #define STATS_REPLY_FLG_BAND_24G_MSK cpu_to_le32(0x2)
2990 #define STATS_REPLY_FLG_HT40_MODE_MSK cpu_to_le32(0x8)
3007 * N_MISSED_BEACONS = 0xa2 (notification only, not a command)
3052 * C_SENSITIVITY = 0xa8 (command, has simple generic response)
3073 * (beacon_energy_[abc] & 0x0FF00) >> 8 (unsigned, higher value is lower level)
3077 * (beacon_silence_rssi_[abc] & 0x0FF00) >> 8 (unsigned, units in dB)
3094 * before and including the latest beacon. Values will wrap around to 0
3121 * (beacon_silence_rssi_[abc] & 0x0FF00), units in dB, across the
3126 * by (beacon_energy_[abc] & 0x0FF00) >> 8, across the 3 receivers,
3139 * Reset this to 0 at the first beacon period that falls within the
3148 * HD_MIN_ENERGY_CCK_DET_IDX 100 / 0 / 100
3164 * down to min 0. Otherwise (if gain has been significantly reduced),
3210 #define HD_MIN_ENERGY_CCK_DET_IDX (0) /* table idxes */
3223 #define C_SENSITIVITY_CONTROL_DEFAULT_TBL cpu_to_le16(0)
3228 * @control: (1) updates working table, (0) updates default table
3239 * C_PHY_CALIBRATION = 0xb0 (command, has simple generic response)
3255 * beacon_rssi_[abc] & 0x0FF (unsigned, units in dB)
3274 * beacon_silence_rssi_[abc] & 0x0FF (unsigned, units in dB)
3277 * will be the reference, with 0 gain adjustment. Attenuate other channels by
3284 * driver should limit the difference results to a range of 0-3 (0-4.5 dB),
3286 * (weakest) chain should be "0".
3289 * 2: (1) reduce gain, (0) increase gain
3290 * 1-0: amount of gain, units of 1.5 dB
3327 * C_LEDS = 0x48 (command, has simple generic response)
3336 * "0", with >0 "on" value, turns LED on */
3338 * "0", regardless of "off", turns LED off */
3348 #define IL_RX_FRAME_SIZE_MSK 0x00003fff