Lines Matching +full:0 +full:x000002a0
44 CMAS_INIT = 0,
60 #define IPW_WAIT (1<<0)
64 #define IPW_POWER_MODE_CAM 0x00 //(always on)
65 #define IPW_POWER_INDEX_1 0x01
66 #define IPW_POWER_INDEX_2 0x02
67 #define IPW_POWER_INDEX_3 0x03
68 #define IPW_POWER_INDEX_4 0x04
69 #define IPW_POWER_INDEX_5 0x05
70 #define IPW_POWER_AC 0x06
71 #define IPW_POWER_BATTERY 0x07
72 #define IPW_POWER_LIMIT 0x07
73 #define IPW_POWER_MASK 0x0F
74 #define IPW_POWER_ENABLED 0x10
135 #define DINO_CMD_WEP_KEY 0x08
136 #define DINO_CMD_TX 0x0B
137 #define DCT_ANTENNA_A 0x01
138 #define DCT_ANTENNA_B 0x02
140 #define IPW_A_MODE 0
149 #define DCT_WEP_KEY_NOT_IMMIDIATE 0x00
150 #define DCT_WEP_KEY_64Bit 0x40
151 #define DCT_WEP_KEY_128Bit 0x80
152 #define DCT_WEP_KEY_128bitIV 0xC0
153 #define DCT_WEP_KEY_SIZE_MASK 0xC0
155 #define DCT_WEP_KEY_INDEX_MASK 0x0F
156 #define DCT_WEP_INDEX_USE_IMMEDIATE 0x20
159 #define DCT_FLAG_ABORT_MGMT 0x01
162 #define DCT_FLAG_CTS_REQUIRED 0x02
165 #define DCT_FLAG_LONG_PREAMBLE 0x00
166 #define DCT_FLAG_SHORT_PREAMBLE 0x04
169 #define DCT_FLAG_RTS_REQD 0x08
172 #define DCT_FLAG_DUR_SET 0x10
175 #define DCT_FLAG_NO_WEP 0x20
178 #define DCT_FLAG_TSF_REQD 0x40
181 #define DCT_FLAG_ACK_REQD 0x80
184 #define DCT_FLAG_EXT_MODE_CCK 0x01
185 #define DCT_FLAG_EXT_MODE_OFDM 0x00
187 #define DCT_FLAG_EXT_SECURITY_WEP 0x00
189 #define DCT_FLAG_EXT_SECURITY_CKIP 0x04
190 #define DCT_FLAG_EXT_SECURITY_CCM 0x08
191 #define DCT_FLAG_EXT_SECURITY_TKIP 0x0C
192 #define DCT_FLAG_EXT_SECURITY_MASK 0x0C
194 #define DCT_FLAG_EXT_QOS_ENABLED 0x10
196 #define DCT_FLAG_EXT_HC_NO_SIFS_PIFS 0x00
197 #define DCT_FLAG_EXT_HC_SIFS 0x20
198 #define DCT_FLAG_EXT_HC_PIFS 0x40
200 #define TX_RX_TYPE_MASK 0xFF
201 #define TX_FRAME_TYPE 0x00
202 #define TX_HOST_COMMAND_TYPE 0x01
203 #define RX_FRAME_TYPE 0x09
204 #define RX_HOST_NOTIFICATION_TYPE 0x03
205 #define RX_HOST_CMD_RESPONSE_TYPE 0x04
206 #define RX_TX_FRAME_RESPONSE_TYPE 0x05
207 #define TFD_NEED_IRQ_MASK 0x04
240 #define DCR_TYPE_AP 0x01
241 #define DCR_TYPE_WLAP 0x02
242 #define DCR_TYPE_MU_ESS 0x03
243 #define DCR_TYPE_MU_IBSS 0x04
244 #define DCR_TYPE_MU_PIBSS 0x05
245 #define DCR_TYPE_SNIFFER 0x06
280 #define QOS_TX0_ACM 0
281 #define QOS_TX1_ACM 0
282 #define QOS_TX2_ACM 0
283 #define QOS_TX3_ACM 0
285 #define QOS_TX0_TXOP_LIMIT_CCK 0
286 #define QOS_TX1_TXOP_LIMIT_CCK 0
290 #define QOS_TX0_TXOP_LIMIT_OFDM 0
291 #define QOS_TX1_TXOP_LIMIT_OFDM 0
315 #define DEF_TX0_AIFS 0
316 #define DEF_TX1_AIFS 0
317 #define DEF_TX2_AIFS 0
318 #define DEF_TX3_AIFS 0
320 #define DEF_TX0_ACM 0
321 #define DEF_TX1_ACM 0
322 #define DEF_TX2_ACM 0
323 #define DEF_TX3_ACM 0
325 #define DEF_TX0_TXOP_LIMIT_CCK 0
326 #define DEF_TX1_TXOP_LIMIT_CCK 0
327 #define DEF_TX2_TXOP_LIMIT_CCK 0
328 #define DEF_TX3_TXOP_LIMIT_CCK 0
330 #define DEF_TX0_TXOP_LIMIT_OFDM 0
331 #define DEF_TX1_TXOP_LIMIT_OFDM 0
332 #define DEF_TX2_TXOP_LIMIT_OFDM 0
333 #define DEF_TX3_TXOP_LIMIT_OFDM 0
336 #define QOS_PARAM_SET_ACTIVE 0
340 #define CTRL_QOS_NO_ACK (0x0020)
455 u8 station_number; /* 0 for BSS */
658 u8 parent_tsf[4]; // fw_use[0] is boolean for OUR_TSF_IS_GREATER
674 u8 rtscts_seen; // 0x1 RTS seen ; 0x2 CTS seen
788 #define DCW_WEP_KEY_INDEX_MASK 0x03 /* bits [0:1] */
789 #define DCW_WEP_KEY_SEC_TYPE_MASK 0x30 /* bits [4:5] */
791 #define DCW_WEP_KEY_SEC_TYPE_WEP 0x00
792 #define DCW_WEP_KEY_SEC_TYPE_CCM 0x20
793 #define DCW_WEP_KEY_SEC_TYPE_TKIP 0x30
795 #define DCW_WEP_KEY_INVALID_SIZE 0x00 /* 0 = Invalid key */
796 #define DCW_WEP_KEY64Bit_SIZE 0x05 /* 64-bit encryption */
797 #define DCW_WEP_KEY128Bit_SIZE 0x0D /* 128-bit encryption */
798 #define DCW_CCM_KEY128Bit_SIZE 0x10 /* 128-bit key */
799 //#define DCW_WEP_KEY128BitIV_SIZE 0x10 /* 128-bit key and 128-bit IV */
828 IPW_SCAN_PASSIVE_TILL_FIRST_BEACON_SCAN = 0,
847 return scan->scan_type[index / 2] & 0x0F; in ipw_get_scan_type()
849 return (scan->scan_type[index / 2] & 0xF0) >> 4; in ipw_get_scan_type()
857 (scan->scan_type[index / 2] & 0xF0) | (scan_type & 0x0F); in ipw_set_scan_type()
860 (scan->scan_type[index / 2] & 0x0F) | in ipw_set_scan_type()
861 ((scan_type & 0x0F) << 4); in ipw_set_scan_type()
1006 #define STATUS_HCMD_ACTIVE (1<<0) /**< host command in progress */
1040 #define CFG_STATIC_CHANNEL (1<<0) /* Restrict assoc. to single channel */
1054 #define CAP_SHARED_KEY (1<<0) /* Off = OPEN */
1058 #define IPW_INVALID_STATION (0xff)
1114 IPW_PROM_CTL_HEADER_ONLY = (1 << 0),
1117 IPW_PROM_ALL_HEADER_ONLY = 0xf, /* bits 0..3 */
1271 u8 eeprom[0x100]; /* 256 bytes of eeprom */
1360 #define BITC(x,y) (((x>>y)&1)?'1':'0')
1363 BITC(x,3),BITC(x,2),BITC(x,1),BITC(x,0)
1380 printk(KERN_DEBUG DRV_NAME": %s " fmt, __func__ , ## args); } while (0)
1385 printk(KERN_DEBUG DRV_NAME": %s " fmt, __func__ , ## args); } while (0)
1387 #define IPW_LL_DEBUG(level, fmt, args...) do {} while (0)
1416 #define IPW_DL_ERROR (1<<0)
1485 #define IPW_INTA_RW 0x00000008
1486 #define IPW_INTA_MASK_R 0x0000000C
1487 #define IPW_INDIRECT_ADDR 0x00000010
1488 #define IPW_INDIRECT_DATA 0x00000014
1489 #define IPW_AUTOINC_ADDR 0x00000018
1490 #define IPW_AUTOINC_DATA 0x0000001C
1491 #define IPW_RESET_REG 0x00000020
1492 #define IPW_GP_CNTRL_RW 0x00000024
1494 #define IPW_READ_INT_REGISTER 0xFF4
1496 #define IPW_GP_CNTRL_BIT_INIT_DONE 0x00000004
1498 #define IPW_REGISTER_DOMAIN1_END 0x00001000
1499 #define IPW_SRAM_READ_INT_REGISTER 0x00000ff4
1501 #define IPW_SHARED_LOWER_BOUND 0x00000200
1502 #define IPW_INTERRUPT_AREA_LOWER_BOUND 0x00000f80
1504 #define IPW_NIC_SRAM_LOWER_BOUND 0x00000000
1505 #define IPW_NIC_SRAM_UPPER_BOUND 0x00030000
1508 #define IPW_GP_CNTRL_BIT_CLOCK_READY 0x00000001
1509 #define IPW_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY 0x00000002
1514 #define CBD_RESET_REG_PRINCETON_RESET (1<<0)
1527 #define IPW_CSR_CIS_UPPER_BOUND 0x00000200
1528 #define IPW_DOMAIN_0_END 0x1000
1529 #define CLX_MEM_BAR_SIZE 0x1000
1533 #define DINO_ENABLE_SYSTEM 0x80 /* 1 = baseband processor on, 0 = reset */
1534 #define DINO_ENABLE_CS 0x40 /* 1 = enable ucode load */
1535 #define DINO_RXFIFO_DATA 0x01 /* 1 = data available */
1536 #define IPW_BASEBAND_CONTROL_STATUS 0X00200000
1537 #define IPW_BASEBAND_TX_FIFO_WRITE 0X00200004
1538 #define IPW_BASEBAND_RX_FIFO_READ 0X00200004
1539 #define IPW_BASEBAND_CONTROL_STORE 0X00200010
1541 #define IPW_INTERNAL_CMD_EVENT 0X00300004
1542 #define IPW_BASEBAND_POWER_DOWN 0x00000001
1544 #define IPW_MEM_HALT_AND_RESET 0x003000e0
1547 #define IPW_BIT_HALT_RESET_ON 0x80000000
1548 #define IPW_BIT_HALT_RESET_OFF 0x00000000
1550 #define CB_LAST_VALID 0x20000000
1551 #define CB_INT_ENABLED 0x40000000
1552 #define CB_VALID 0x80000000
1553 #define CB_SRC_LE 0x08000000
1554 #define CB_DEST_LE 0x04000000
1555 #define CB_SRC_AUTOINC 0x00800000
1556 #define CB_SRC_IO_GATED 0x00400000
1557 #define CB_DEST_AUTOINC 0x00080000
1558 #define CB_SRC_SIZE_LONG 0x00200000
1559 #define CB_DEST_SIZE_LONG 0x00020000
1563 #define DMA_CONTROL_SMALL_CB_CONST_VALUE 0x00540000
1564 #define DMA_CB_STOP_AND_ABORT 0x00000C00
1565 #define DMA_CB_START 0x00000100
1567 #define IPW_SHARED_SRAM_SIZE 0x00030000
1568 #define IPW_SHARED_SRAM_DMA_CONTROL 0x00027000
1569 #define CB_MAX_LENGTH 0x1FFF
1571 #define IPW_HOST_EEPROM_DATA_SRAM_SIZE 0xA18
1572 #define IPW_EEPROM_IMAGE_SIZE 0x100
1575 #define IPW_DMA_I_CURRENT_CB 0x003000D0
1576 #define IPW_DMA_O_CURRENT_CB 0x003000D4
1577 #define IPW_DMA_I_DMA_CONTROL 0x003000A4
1578 #define IPW_DMA_I_CB_BASE 0x003000A0
1580 #define IPW_TX_CMD_QUEUE_BD_BASE 0x00000200
1581 #define IPW_TX_CMD_QUEUE_BD_SIZE 0x00000204
1582 #define IPW_TX_QUEUE_0_BD_BASE 0x00000208
1583 #define IPW_TX_QUEUE_0_BD_SIZE (0x0000020C)
1584 #define IPW_TX_QUEUE_1_BD_BASE 0x00000210
1585 #define IPW_TX_QUEUE_1_BD_SIZE 0x00000214
1586 #define IPW_TX_QUEUE_2_BD_BASE 0x00000218
1587 #define IPW_TX_QUEUE_2_BD_SIZE (0x0000021C)
1588 #define IPW_TX_QUEUE_3_BD_BASE 0x00000220
1589 #define IPW_TX_QUEUE_3_BD_SIZE 0x00000224
1590 #define IPW_RX_BD_BASE 0x00000240
1591 #define IPW_RX_BD_SIZE 0x00000244
1592 #define IPW_RFDS_TABLE_LOWER 0x00000500
1594 #define IPW_TX_CMD_QUEUE_READ_INDEX 0x00000280
1595 #define IPW_TX_QUEUE_0_READ_INDEX 0x00000284
1596 #define IPW_TX_QUEUE_1_READ_INDEX 0x00000288
1597 #define IPW_TX_QUEUE_2_READ_INDEX (0x0000028C)
1598 #define IPW_TX_QUEUE_3_READ_INDEX 0x00000290
1599 #define IPW_RX_READ_INDEX (0x000002A0)
1601 #define IPW_TX_CMD_QUEUE_WRITE_INDEX (0x00000F80)
1602 #define IPW_TX_QUEUE_0_WRITE_INDEX (0x00000F84)
1603 #define IPW_TX_QUEUE_1_WRITE_INDEX (0x00000F88)
1604 #define IPW_TX_QUEUE_2_WRITE_INDEX (0x00000F8C)
1605 #define IPW_TX_QUEUE_3_WRITE_INDEX (0x00000F90)
1606 #define IPW_RX_WRITE_INDEX (0x00000FA0)
1612 #define IPW_EEPROM_DATA_SRAM_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x814)
1613 #define IPW_EEPROM_DATA_SRAM_SIZE (IPW_SHARED_LOWER_BOUND + 0x818)
1614 #define IPW_EEPROM_LOAD_DISABLE (IPW_SHARED_LOWER_BOUND + 0x81C)
1615 #define IPW_EEPROM_DATA (IPW_SHARED_LOWER_BOUND + 0x820)
1616 #define IPW_EEPROM_UPPER_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x9E0)
1618 #define IPW_STATION_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0xA0C)
1619 #define IPW_STATION_TABLE_UPPER (IPW_SHARED_LOWER_BOUND + 0xB0C)
1620 #define IPW_REQUEST_ATIM (IPW_SHARED_LOWER_BOUND + 0xB0C)
1621 #define IPW_ATIM_SENT (IPW_SHARED_LOWER_BOUND + 0xB10)
1622 #define IPW_WHO_IS_AWAKE (IPW_SHARED_LOWER_BOUND + 0xB14)
1623 #define IPW_DURING_ATIM_WINDOW (IPW_SHARED_LOWER_BOUND + 0xB18)
1626 #define LSB 0
1633 #define EEPROM_PME_CAPABILITY (GET_EEPROM_ADDR(0x09,MSB)) /* 1 byte */
1634 #define EEPROM_MAC_ADDRESS (GET_EEPROM_ADDR(0x21,LSB)) /* 6 byte */
1635 #define EEPROM_VERSION (GET_EEPROM_ADDR(0x24,MSB)) /* 1 byte */
1636 #define EEPROM_NIC_TYPE (GET_EEPROM_ADDR(0x25,LSB)) /* 1 byte */
1637 #define EEPROM_SKU_CAPABILITY (GET_EEPROM_ADDR(0x25,MSB)) /* 1 byte */
1638 #define EEPROM_COUNTRY_CODE (GET_EEPROM_ADDR(0x26,LSB)) /* 3 bytes */
1639 #define EEPROM_IBSS_CHANNELS_BG (GET_EEPROM_ADDR(0x28,LSB)) /* 2 bytes */
1640 #define EEPROM_IBSS_CHANNELS_A (GET_EEPROM_ADDR(0x29,MSB)) /* 5 bytes */
1641 #define EEPROM_BSS_CHANNELS_BG (GET_EEPROM_ADDR(0x2c,LSB)) /* 2 bytes */
1642 #define EEPROM_HW_VERSION (GET_EEPROM_ADDR(0x72,LSB)) /* 2 bytes */
1645 #define EEPROM_NIC_TYPE_0 0
1652 #define EEPROM_SKU_CAP_BT_CHANNEL_SIG 0x01 /* we can tell BT our channel # */
1653 #define EEPROM_SKU_CAP_BT_PRIORITY 0x02 /* BT can take priority over us */
1654 #define EEPROM_SKU_CAP_BT_OOB 0x04 /* we can signal BT out-of-band */
1656 #define FW_MEM_REG_LOWER_BOUND 0x00300000
1657 #define FW_MEM_REG_EEPROM_ACCESS (FW_MEM_REG_LOWER_BOUND + 0x40)
1658 #define IPW_EVENT_REG (FW_MEM_REG_LOWER_BOUND + 0x04)
1659 #define EEPROM_BIT_SK (1<<0)
1664 #define EEPROM_CMD_READ 0x2
1667 #define IPW_INTA_NONE 0x00000000
1669 #define IPW_INTA_BIT_RX_TRANSFER 0x00000002
1670 #define IPW_INTA_BIT_STATUS_CHANGE 0x00000010
1671 #define IPW_INTA_BIT_BEACON_PERIOD_EXPIRED 0x00000020
1674 #define IPW_INTA_BIT_TX_CMD_QUEUE 0x00000800
1675 #define IPW_INTA_BIT_TX_QUEUE_1 0x00001000
1676 #define IPW_INTA_BIT_TX_QUEUE_2 0x00002000
1677 #define IPW_INTA_BIT_TX_QUEUE_3 0x00004000
1678 #define IPW_INTA_BIT_TX_QUEUE_4 0x00008000
1680 #define IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE 0x00010000
1682 #define IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN 0x00100000
1683 #define IPW_INTA_BIT_POWER_DOWN 0x00200000
1685 #define IPW_INTA_BIT_FW_INITIALIZATION_DONE 0x01000000
1686 #define IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE 0x02000000
1687 #define IPW_INTA_BIT_RF_KILL_DONE 0x04000000
1688 #define IPW_INTA_BIT_FATAL_ERROR 0x40000000
1689 #define IPW_INTA_BIT_PARITY_ERROR 0x80000000
1723 IPW_FW_ERROR_OK = 0,
1740 #define AUTH_OPEN 0
1745 #define HC_ASSOCIATE 0
1752 #define HC_QOS_SUPPORT_ASSOC cpu_to_le16(0x01)
1755 #define IPW_RATE_CONNECT 0
1760 #define IPW_TX_RATE_1MB 0x0A
1761 #define IPW_TX_RATE_2MB 0x14
1762 #define IPW_TX_RATE_5MB 0x37
1763 #define IPW_TX_RATE_6MB 0x0D
1764 #define IPW_TX_RATE_9MB 0x0F
1765 #define IPW_TX_RATE_11MB 0x6E
1766 #define IPW_TX_RATE_12MB 0x05
1767 #define IPW_TX_RATE_18MB 0x07
1768 #define IPW_TX_RATE_24MB 0x09
1769 #define IPW_TX_RATE_36MB 0x0B
1770 #define IPW_TX_RATE_48MB 0x01
1771 #define IPW_TX_RATE_54MB 0x03
1773 #define IPW_ORD_TABLE_ID_MASK 0x0000FF00
1774 #define IPW_ORD_TABLE_VALUE_MASK 0x000000FF
1776 #define IPW_ORD_TABLE_0_MASK 0x0000F000
1777 #define IPW_ORD_TABLE_1_MASK 0x0000F100
1778 #define IPW_ORD_TABLE_2_MASK 0x0000F200
1779 #define IPW_ORD_TABLE_3_MASK 0x0000F300
1780 #define IPW_ORD_TABLE_4_MASK 0x0000F400
1781 #define IPW_ORD_TABLE_5_MASK 0x0000F500
1782 #define IPW_ORD_TABLE_6_MASK 0x0000F600
1783 #define IPW_ORD_TABLE_7_MASK 0x0000F700
1786 * Table 0 Entries (all entries are 32 bits)
1877 IPW_ORD_STAT_TX_PACKET = IPW_ORD_TABLE_3_MASK | 0,
1924 #define IPW_ERROR_LOG (IPW_SHARED_LOWER_BOUND + 0x410)
1925 #define IPW_EVENT_LOG (IPW_SHARED_LOWER_BOUND + 0x414)
1926 #define IPW_ORDINALS_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0x500)
1927 #define IPW_ORDINALS_TABLE_0 (IPW_SHARED_LOWER_BOUND + 0x180)
1928 #define IPW_ORDINALS_TABLE_1 (IPW_SHARED_LOWER_BOUND + 0x184)
1929 #define IPW_ORDINALS_TABLE_2 (IPW_SHARED_LOWER_BOUND + 0x188)
1930 #define IPW_MEM_FIXED_OVERRIDE (IPW_SHARED_LOWER_BOUND + 0x41C)
1937 #define IPW_INDIRECT_ADDR_MASK (~0x3ul)
1961 #define CFG_BT_COEXISTENCE_SIGNAL_CHNL 0x01 /* tell BT our chnl # */
1962 #define CFG_BT_COEXISTENCE_DEFER 0x02 /* defer our Tx if BT traffic */
1963 #define CFG_BT_COEXISTENCE_KILL 0x04 /* kill our Tx if BT traffic */
1964 #define CFG_BT_COEXISTENCE_WME_OVER_BT 0x08 /* multimedia extensions */
1965 #define CFG_BT_COEXISTENCE_OOB 0x10 /* signal BT via out-of-band */
1968 #define CFG_CTS_TO_ITSELF_ENABLED_MIN 0x00
1969 #define CFG_CTS_TO_ITSELF_ENABLED_MAX 0x01
1973 #define CFG_SYS_ANTENNA_BOTH 0x00 /* NIC selects best antenna */
1974 #define CFG_SYS_ANTENNA_A 0x01 /* force antenna A */
1975 #define CFG_SYS_ANTENNA_B 0x03 /* force antenna B */
1976 #define CFG_SYS_ANTENNA_SLOW_DIV 0x02 /* consider background noise */