Lines Matching +full:rev +full:- +full:mii
1 // SPDX-License-Identifier: ISC
30 u32 chipcontrol; /* 0x28, rev >= 11 */
31 u32 chipstatus; /* 0x2c, rev >= 11 */
34 u32 jtagcmd; /* 0x30, rev >= 10 */
49 /* gpio - cleared only by power-on-reset */
77 u32 clockcontrol_m2; /* mii/uart/mipsref */
199 u32 gpiosel; /* 0x638, rev >= 1 */
200 u32 gpioenable; /* 0x63c, rev >= 1 */
234 #define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
251 #define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */
252 #define CC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */
253 #define CC_CAP_SROM 0x40000000 /* Srom Present, rev >= 32 */
254 /* Nand flash present, rev >= 35 */
257 #define CC_CAP2_SECI 0x00000001 /* SECI Present, rev >= 36 */
258 /* GSIO (spi/i2c) present, rev >= 37 */
261 /* sr_control0, rev >= 48 */
298 /* pmucapabilites_ext PMU rev >= 15 */
300 /* retention_ctl PMU rev >= 15 */