Lines Matching +full:suppress +full:- +full:preamble
32 #define TX_AC_BE_FIFO 1 /* Best-Effort TX FIFO */
60 /* 2byte-wide pio register set per channel(xmt or rcv) */
74 /* 4byte-wide pio register set per channel(xmt or rcv) */
86 /* read: 32-bit register that can be read as 32-bit or as 2 16-bit
87 * write: only low 16b-it half can be written
108 /* Device Control ("semi-standard host registers") */
109 u32 PAD[3]; /* 0x0 - 0x8 */
119 u32 PAD[40]; /* 0x60 - 0xFC */
121 u32 intrcvlazy[4]; /* 0x100 - 0x10C */
123 u32 PAD[4]; /* 0x110 - 0x11c */
133 u32 PAD[2]; /* 0x138 - 0x13C */
149 u32 PAD[2]; /* 0x168 - 0x16c */
153 u32 PAD[2]; /* 0x178 - 0x17c */
161 u32 PAD[3]; /* 0x194 - 0x19c */
165 u32 PAD[14]; /* 0x1a8 - 0x1dc */
173 u32 PAD[5]; /* 0x1ec - 0x1fc */
175 /* 0x200-0x37F dma/pio registers */
179 struct dma32diag dmafifo; /* 0x380 - 0x38C */
183 u32 PAD[16]; /* 0x398 - 0x3d4 */
194 u16 phyversion; /* 0x3e0 - 0x0 */
195 u16 phybbconfig; /* 0x3e2 - 0x1 */
196 u16 phyadcbias; /* 0x3e4 - 0x2 Bphy only */
197 u16 phyanacore; /* 0x3e6 - 0x3 pwwrdwn on aphy */
198 u16 phyrxstatus0; /* 0x3e8 - 0x4 */
199 u16 phyrxstatus1; /* 0x3ea - 0x5 */
200 u16 phycrsth; /* 0x3ec - 0x6 */
201 u16 phytxerror; /* 0x3ee - 0x7 */
202 u16 phychannel; /* 0x3f0 - 0x8 */
203 u16 PAD[1]; /* 0x3f2 - 0x9 */
204 u16 phytest; /* 0x3f4 - 0xa */
205 u16 phy4waddr; /* 0x3f6 - 0xb */
206 u16 phy4wdatahi; /* 0x3f8 - 0xc */
207 u16 phy4wdatalo; /* 0x3fa - 0xd */
208 u16 phyregaddr; /* 0x3fc - 0xe */
209 u16 phyregdata; /* 0x3fe - 0xf */
211 /* IHR *//* 0x400 - 0x7FE */
214 u16 PAD[3]; /* 0x400 - 0x406 */
216 u16 PAD; /* 0x408 - 0x40a */
218 u16 PAD[4]; /* 0x40a - 0x414 */
220 u16 PAD[5]; /* 0x414 - 0x420 */
239 u16 PAD[30]; /* 0x444 - 0x480 */
241 /* PSM Block *//* 0x480 - 0x500 */
288 u16 PAD[0xD]; /* 0x4D6 - 0x4DE */
290 u16 PAD[0x7]; /* 0x4f2 - 0x4fE */
292 /* TXE0 Block *//* 0x500 - 0x580 */
305 u16 PAD[0x05]; /* 0x510 - 0x51E */
316 u16 PAD[0x09]; /* 0x52E - 0x53E */
330 u16 PAD[0x04]; /* 0x558 - 0x55E */
334 u16 PAD[2]; /* 0x564 - 0x566 */
340 u16 PAD[0x09]; /* 0x56E - 0x57E */
343 u16 PAD[0x40]; /* 0x580 - 0x5FE */
346 u16 PAD[0X02]; /* 0x600 - 0x602 */
349 u16 PAD[0X05]; /* 0x608 - 0x610 */
351 u16 PAD[0XD]; /* 0x614 - 0x62C */
354 u16 PAD[0X14]; /* 0x632 - 0x658 */
356 u16 PAD[0x05]; /* 0x65C - 0x664 */
364 u16 PAD[0x07]; /* 0x672 - 0x67E */
372 u16 PAD[0x3]; /* 0x68a - 0x68F */
376 u16 PAD[0x3]; /* 0x696 - 0x69b */
398 u16 PAD[0x3e]; /* 0x702 - 0x77E */
400 /* WEP/PMQ Block *//* 0x780 - 0x7FE */
401 u16 PAD[0x20]; /* 0x780 - 0x7BE */
408 u16 PAD[4]; /* 0x7C8 - 0x7CE */
411 u16 PAD[6]; /* 0x7D4 - 0x7DE */
427 u16 PAD[0x04]; /* 0x7F8 - 0x7FE */
429 /* SHM *//* 0x800 - 0xEFE */
430 u16 PAD[0x380]; /* 0x800 - 0xEFE */
502 /* end of ATIM-window (IBSS) */
506 /* non-specific gen-stat bits that are set by PSM */
508 /* non-specific gen-stat bits that are set by PSM */
512 /* non-specific gen-stat bits that are set by PSM */
518 /* General-purpose timer0 */
520 /* General-purpose timer1 */
522 /* (ORed) DMA-interrupts */
561 /* Dis-associated or De-authenticated */
567 /* delete head entry to cur read pointer -1 */
583 /* phy detected the end of a valid frame preamble */
661 #define PHY_TYPE_N 4 /* N-Phy value */
662 #define PHY_TYPE_SSN 6 /* SSLPN-Phy value */
663 #define PHY_TYPE_LCN 8 /* LCN-Phy value */
664 #define PHY_TYPE_LCNXN 9 /* LCNXN-Phy value */
677 #define D11A_PHY_HDR_GRATE(phdr) ((phdr)->rlpt[0] & 0x0f)
678 #define D11A_PHY_HDR_GRES(phdr) (((phdr)->rlpt[0] >> 4) & 0x01)
679 #define D11A_PHY_HDR_GLENGTH(phdr) (((u32 *)((phdr)->rlpt) >> 5) & 0x0fff)
680 #define D11A_PHY_HDR_GPARITY(phdr) (((phdr)->rlpt[3] >> 1) & 0x01)
681 #define D11A_PHY_HDR_GTAIL(phdr) (((phdr)->rlpt[3] >> 2) & 0x3f)
683 /* rate encoded per 802.11a-1999 sec 17.3.4.1 */
685 ((phdr)->rlpt[0] = ((phdr)->rlpt[0] & 0xf0) | ((rate) & 0xf))
687 #define D11A_PHY_HDR_SRES(phdr) ((phdr)->rlpt[0] &= 0xef)
690 (*(u32 *)((phdr)->rlpt) = *(u32 *)((phdr)->rlpt) | \
693 #define D11A_PHY_HDR_STAIL(phdr) ((phdr)->rlpt[3] &= 0x03)
695 #define D11A_PHY_HDR_LEN_L 3 /* low-rate part of PLCP header */
696 #define D11A_PHY_HDR_LEN_R 2 /* high-rate part of PLCP header */
700 #define D11A_PHY_HDR_TIME (4) /* low-rate part of PLCP header */
763 u8 IV[16]; /* 0x0b - 0x12 */
764 u8 TxFrameRA[6]; /* 0x13 - 0x15 */
766 u8 RTSPLCPFallback[6]; /* 0x17 - 0x19 */
768 u8 FragPLCPFallback[6]; /* 0x1b - 1d */
783 u8 RTSPhyHeader[D11_PHY_HDR_LEN]; /* 0x2c - 0x2e */
784 struct ieee80211_rts rts_frame; /* 0x2f - 0x36 */
797 * Position of MPDU inside A-MPDU; indicated with bits 10:9
801 #define TXC_AMPDU_NONE 0 /* Regular MPDU, not an A-MPDU */
802 #define TXC_AMPDU_FIRST 1 /* first MPDU of an A-MPDU */
803 #define TXC_AMPDU_MIDDLE 2 /* intermediate MPDU of an A-MPDU */
804 #define TXC_AMPDU_LAST 3 /* last (or single) MPDU of an A-MPDU */
821 /* RTS fallback preamble type 1 = SHORT 0 = LONG */
823 /* RTS main rate preamble type 1 = SHORT 0 = LONG */
826 * Main fallback rate preamble type
878 #define PHY_TXC_HTANT_MASK 0x3fC0 /* bits 6-13 */
926 #define TX_STATUS_SUPR_MASK 0x1C /* suppress status bits (4:2) */
932 /* suppress status reason codes */
946 /* Unexpected tx status for A-MPDU rate update */
1000 #define ADDR_BMP_AP (1 << 3) /* Infra-BSS Access Point */
1001 #define ADDR_BMP_STA (1 << 4) /* Infra-BSS Station */
1094 /* PS-mode related parameters */
1099 /* Beacon-related parameters */
1121 /* Rx-related parameters */
1320 #define MHFMAX 5 /* Number of valid hostflag half-word (u16) */
1371 * Receive Frame Data Header for 802.11b DCF-only frames
1428 /* Short Preamble */
1442 /* valid only for G phy, use rxh->RxChan for A phy */
1504 ((((rxs)->PhyRxStatus_1 & PRXS1_HTPHY_MMPLCPLenL_MASK) >> 8) | \
1505 (((rxs)->PhyRxStatus_2 & PRXS2_HTPHY_MMPLCPLenH_MASK) << 8))
1508 ((((rxs)->PhyRxStatus_2) & PRXS2_HTPHY_RXPWR_ANT0) >> 8)
1511 (((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT1)
1514 ((((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT2) >> 8)
1562 #define M_SYNTHPU_DLY (0x4a * 2) /* pre-wakeup for synthpu, default: 500 */
1592 /* offset 0x03: scratch registers for Dot11-contants */
1593 S_DOT11_CWMIN, /* CW-minimum */
1594 S_DOT11_CWMAX, /* CW-maximum */
1595 S_DOT11_CWCUR, /* CW-current */
1598 S_DOT11_DTIMCOUNT, /* DTIM-count */
1600 /* offset 0x09: Tx-side scratch registers */
1608 S_OLD_CWWIN, /* saved-off CW-cur */
1609 S_TXECTL, /* TXE-Ctl word constructed in scr-pad */
1610 S_CTXTST, /* frm type-subtype as read from Tx-descr */
1612 /* offset 0x13: Rx-side scratch registers */
1621 S_THIS_AGG, /* Size of this AGG (A-MSDU) */
1631 S_RXSSN, /* Received start seq number for A-MPDU BA */
1632 S_RXQOSFLD, /* Rx-QoS field (if present) */
1651 S_CUR_PTR, /* Temp pointer for A-MPDU re-Tx SHM table */
1663 S_RXESN, /* Received end sequence number for A-MPDU BA */
1684 u16 txfunfl[8]; /* 0x8c - 0x9b */
1737 /* dot11 core-specific control flags */
1751 /* dot11 core-specific status flags */