Lines Matching +full:0 +full:x3e000000
35 #define SCC_SS_MASK 0x00000007
37 #define SCC_SS_LPO 0x00000000
39 #define SCC_SS_XTAL 0x00000001
41 #define SCC_SS_PCI 0x00000002
42 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
43 #define SCC_LF 0x00000200
44 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
45 #define SCC_LP 0x00000400
46 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
47 #define SCC_FS 0x00000800
48 /* IgnorePllOffReq, 1/0:
51 #define SCC_IP 0x00001000
52 /* XtalControlEn, 1/0:
55 #define SCC_XC 0x00002000
56 /* XtalPU (RO), 1/0: crystal running/disabled */
57 #define SCC_XP 0x00004000
59 #define SCC_CD_MASK 0xffff0000
64 #define SYCC_IE 0x00000001
66 #define SYCC_AE 0x00000002
68 #define SYCC_FP 0x00000004
70 #define SYCC_AR 0x00000008
72 #define SYCC_HR 0x00000010
74 #define SYCC_CD_MASK 0xffff0000
77 #define CST4329_SPROM_OTP_SEL_MASK 0x00000003
79 #define CST4329_DEFCIS_SEL 0
87 #define CST4329_SPI_SDIO_MODE_MASK 0x00000004
91 #define CCTRL43224_GPIO_TOGGLE 0x8000
93 #define CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0
95 #define CCTRL_43224B0_12MA_LED_DRIVE 0xF0
98 #define CST43236_SFLASH_MASK 0x00000040
99 #define CST43236_OTP_MASK 0x00000080
100 #define CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */
101 #define CST43236_BP_CLK 0x00000200 /* 120/96Mbps */
102 #define CST43236_BOOT_MASK 0x00001800
104 #define CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */
110 /* 0 disable */
111 #define CCTRL4331_BT_COEXIST (1<<0)
112 /* 0 SECI is disabled (JTAG functional) */
114 /* 0 disable */
118 /* 0 ext pa disable, 1 ext pa enabled */
141 #define CST4331_XTAL_FREQ 0x00000001
142 #define CST4331_SPROM_PRESENT 0x00000002
143 #define CST4331_OTP_PRESENT 0x00000004
144 #define CST4331_LDO_RF 0x00000008
145 #define CST4331_LDO_PAR 0x00000010
148 #define CST4319_SPI_CPULESSUSB 0x00000001
149 #define CST4319_SPI_CLK_POL 0x00000002
150 #define CST4319_SPI_CLK_PH 0x00000008
152 #define CST4319_SPROM_OTP_SEL_MASK 0x000000c0
155 #define CST4319_DEFCIS_SEL 0x00000000
157 #define CST4319_SPROM_SEL 0x00000040
159 #define CST4319_OTP_SEL 0x00000080
161 #define CST4319_OTP_PWRDN 0x000000c0
163 #define CST4319_SDIO_USB_MODE 0x00000100
164 #define CST4319_REMAP_SEL_MASK 0x00000600
165 #define CST4319_ILPDIV_EN 0x00000800
166 #define CST4319_XTAL_PD_POL 0x00001000
167 #define CST4319_LPO_SEL 0x00002000
168 #define CST4319_RES_INIT_MODE 0x0000c000
170 #define CST4319_PALDO_EXTPNP 0x00010000
171 #define CST4319_CBUCK_MODE_MASK 0x00060000
172 #define CST4319_CBUCK_MODE_BURST 0x00020000
173 #define CST4319_CBUCK_MODE_LPBURST 0x00060000
174 #define CST4319_RCAL_VALID 0x01000000
175 #define CST4319_RCAL_VALUE_MASK 0x3e000000
179 #define CST4336_SPI_MODE_MASK 0x00000001
180 #define CST4336_SPROM_PRESENT 0x00000002
181 #define CST4336_OTP_PRESENT 0x00000004
182 #define CST4336_ARMREMAP_0 0x00000008
183 #define CST4336_ILPDIV_EN_MASK 0x00000010
185 #define CST4336_XTAL_PD_POL_MASK 0x00000020
187 #define CST4336_LPO_SEL_MASK 0x00000040
189 #define CST4336_RES_INIT_MODE_MASK 0x00000180
191 #define CST4336_CBUCK_MODE_MASK 0x00000600
197 #define CST4313_SPROM_OTP_SEL_MASK 0x00000002
198 #define CST4313_SPROM_OTP_SEL_SHIFT 0
202 #define CCTRL_4313_12MA_LED_DRIVE 0x00000007
205 #define MFGID_ARM 0x43b
206 #define MFGID_BRCM 0x4bf
207 #define MFGID_MIPS 0x4a7
210 #define ER_EROMENTRY 0x000
211 #define ER_REMAPCONTROL 0xe00
212 #define ER_REMAPSELECT 0xe04
213 #define ER_MASTERSELECT 0xe10
214 #define ER_ITCR 0xf00
215 #define ER_ITIP 0xf04
218 #define ER_TAG 0xe
219 #define ER_TAG1 0x6
221 #define ER_CI 0
224 #define ER_END 0xe
225 #define ER_BAD 0xffffffff
228 #define CIA_MFG_MASK 0xfff00000
230 #define CIA_CID_MASK 0x000fff00
232 #define CIA_CCL_MASK 0x000000f0
236 #define CIB_REV_MASK 0xff000000
238 #define CIB_NSW_MASK 0x00f80000
240 #define CIB_NMW_MASK 0x0007c000
242 #define CIB_NSP_MASK 0x00003e00
244 #define CIB_NMP_MASK 0x000001f0
248 #define AD_ADDR_MASK 0xfffff000
249 #define AD_SP_MASK 0x00000f00
251 #define AD_ST_MASK 0x000000c0
253 #define AD_ST_SLAVE 0x00000000
254 #define AD_ST_BRIDGE 0x00000040
255 #define AD_ST_SWRAP 0x00000080
256 #define AD_ST_MWRAP 0x000000c0
257 #define AD_SZ_MASK 0x00000030
259 #define AD_SZ_4K 0x00000000
260 #define AD_SZ_8K 0x00000010
261 #define AD_SZ_16K 0x00000020
262 #define AD_SZ_SZD 0x00000030
263 #define AD_AG32 0x00000008
264 #define AD_ADDR_ALIGN 0x00000fff
265 #define AD_SZ_BASE 0x00001000 /* 4KB */
268 #define SD_SZ_MASK 0xfffff000
269 #define SD_SG32 0x00000008
270 #define SD_SZ_ALIGN 0x00000fff
273 #define PCI_CFG_GPIO_SCS 0x10
275 #define PCI_CFG_GPIO_XTAL 0x40
277 #define PCI_CFG_GPIO_PLL 0x80
294 #define SRC_START 0x80000000
295 #define SRC_BUSY 0x80000000
296 #define SRC_OPCODE 0x60000000
297 #define SRC_OP_READ 0x00000000
298 #define SRC_OP_WRITE 0x20000000
299 #define SRC_OP_WRDIS 0x40000000
300 #define SRC_OP_WREN 0x60000000
301 #define SRC_OTPSEL 0x00000010
302 #define SRC_LOCK 0x00000008
303 #define SRC_SIZE_MASK 0x00000006
304 #define SRC_SIZE_1K 0x00000000
305 #define SRC_SIZE_4K 0x00000002
306 #define SRC_SIZE_16K 0x00000004
308 #define SRC_PRESENT 0x00000001
311 #define GPIO_CTRL_EPA_EN_MASK 0x40
326 u32 oobselina30; /* 0x000 */
327 u32 oobselina74; /* 0x004 */
329 u32 oobselinb30; /* 0x020 */
330 u32 oobselinb74; /* 0x024 */
332 u32 oobselinc30; /* 0x040 */
333 u32 oobselinc74; /* 0x044 */
335 u32 oobselind30; /* 0x060 */
336 u32 oobselind74; /* 0x064 */
338 u32 oobselouta30; /* 0x100 */
339 u32 oobselouta74; /* 0x104 */
341 u32 oobseloutb30; /* 0x120 */
342 u32 oobseloutb74; /* 0x124 */
344 u32 oobseloutc30; /* 0x140 */
345 u32 oobseloutc74; /* 0x144 */
347 u32 oobseloutd30; /* 0x160 */
348 u32 oobseloutd74; /* 0x164 */
350 u32 oobsynca; /* 0x200 */
351 u32 oobseloutaen; /* 0x204 */
353 u32 oobsyncb; /* 0x220 */
354 u32 oobseloutben; /* 0x224 */
356 u32 oobsyncc; /* 0x240 */
357 u32 oobseloutcen; /* 0x244 */
359 u32 oobsyncd; /* 0x260 */
360 u32 oobseloutden; /* 0x264 */
362 u32 oobaextwidth; /* 0x300 */
363 u32 oobainwidth; /* 0x304 */
364 u32 oobaoutwidth; /* 0x308 */
366 u32 oobbextwidth; /* 0x320 */
367 u32 oobbinwidth; /* 0x324 */
368 u32 oobboutwidth; /* 0x328 */
370 u32 oobcextwidth; /* 0x340 */
371 u32 oobcinwidth; /* 0x344 */
372 u32 oobcoutwidth; /* 0x348 */
374 u32 oobdextwidth; /* 0x360 */
375 u32 oobdinwidth; /* 0x364 */
376 u32 oobdoutwidth; /* 0x368 */
378 u32 ioctrlset; /* 0x400 */
379 u32 ioctrlclear; /* 0x404 */
380 u32 ioctrl; /* 0x408 */
382 u32 iostatus; /* 0x500 */
384 u32 ioctrlwidth; /* 0x700 */
385 u32 iostatuswidth; /* 0x704 */
387 u32 resetctrl; /* 0x800 */
388 u32 resetstatus; /* 0x804 */
389 u32 resetreadid; /* 0x808 */
390 u32 resetwriteid; /* 0x80c */
392 u32 errlogctrl; /* 0x900 */
393 u32 errlogdone; /* 0x904 */
394 u32 errlogstatus; /* 0x908 */
395 u32 errlogaddrlo; /* 0x90c */
396 u32 errlogaddrhi; /* 0x910 */
397 u32 errlogid; /* 0x914 */
398 u32 errloguser; /* 0x918 */
399 u32 errlogflags; /* 0x91c */
401 u32 intstatus; /* 0xa00 */
403 u32 config; /* 0xe00 */
405 u32 itcr; /* 0xf00 */
407 u32 itipooba; /* 0xf10 */
408 u32 itipoobb; /* 0xf14 */
409 u32 itipoobc; /* 0xf18 */
410 u32 itipoobd; /* 0xf1c */
412 u32 itipoobaout; /* 0xf30 */
413 u32 itipoobbout; /* 0xf34 */
414 u32 itipoobcout; /* 0xf38 */
415 u32 itipoobdout; /* 0xf3c */
417 u32 itopooba; /* 0xf50 */
418 u32 itopoobb; /* 0xf54 */
419 u32 itopoobc; /* 0xf58 */
420 u32 itopoobd; /* 0xf5c */
422 u32 itopoobain; /* 0xf70 */
423 u32 itopoobbin; /* 0xf74 */
424 u32 itopoobcin; /* 0xf78 */
425 u32 itopoobdin; /* 0xf7c */
427 u32 itopreset; /* 0xf90 */
429 u32 peripherialid4; /* 0xfd0 */
430 u32 peripherialid5; /* 0xfd4 */
431 u32 peripherialid6; /* 0xfd8 */
432 u32 peripherialid7; /* 0xfdc */
433 u32 peripherialid0; /* 0xfe0 */
434 u32 peripherialid1; /* 0xfe4 */
435 u32 peripherialid2; /* 0xfe8 */
436 u32 peripherialid3; /* 0xfec */
437 u32 componentid0; /* 0xff0 */
438 u32 componentid1; /* 0xff4 */
439 u32 componentid2; /* 0xff8 */
440 u32 componentid3; /* 0xffc */
447 if (cc->bus->nr_cores == 0) in ai_buscore_setup()
491 bcma_write32(cc, CHIPCREGOFFS(gpiopullup), 0); in ai_doattach()
492 bcma_write32(cc, CHIPCREGOFFS(gpiopulldown), 0); in ai_doattach()
647 return 0; in ai_clkctl_fast_pwrup_delay()
649 fpdelay = 0; in ai_clkctl_fast_pwrup_delay()
694 u32 w = 0; in ai_deviceremoved()
703 if ((w & 0xFFFF) != PCI_VENDOR_ID_BROADCOM) in ai_deviceremoved()