Lines Matching +full:0 +full:x422
30 #define B43legacy_MMIO_DMA0_REASON 0x20
31 #define B43legacy_MMIO_DMA0_IRQ_MASK 0x24
32 #define B43legacy_MMIO_DMA1_REASON 0x28
33 #define B43legacy_MMIO_DMA1_IRQ_MASK 0x2C
34 #define B43legacy_MMIO_DMA2_REASON 0x30
35 #define B43legacy_MMIO_DMA2_IRQ_MASK 0x34
36 #define B43legacy_MMIO_DMA3_REASON 0x38
37 #define B43legacy_MMIO_DMA3_IRQ_MASK 0x3C
38 #define B43legacy_MMIO_DMA4_REASON 0x40
39 #define B43legacy_MMIO_DMA4_IRQ_MASK 0x44
40 #define B43legacy_MMIO_DMA5_REASON 0x48
41 #define B43legacy_MMIO_DMA5_IRQ_MASK 0x4C
42 #define B43legacy_MMIO_MACCTL 0x120 /* MAC control */
43 #define B43legacy_MMIO_MACCMD 0x124 /* MAC command */
44 #define B43legacy_MMIO_GEN_IRQ_REASON 0x128
45 #define B43legacy_MMIO_GEN_IRQ_MASK 0x12C
46 #define B43legacy_MMIO_RAM_CONTROL 0x130
47 #define B43legacy_MMIO_RAM_DATA 0x134
48 #define B43legacy_MMIO_PS_STATUS 0x140
49 #define B43legacy_MMIO_RADIO_HWENABLED_HI 0x158
50 #define B43legacy_MMIO_SHM_CONTROL 0x160
51 #define B43legacy_MMIO_SHM_DATA 0x164
52 #define B43legacy_MMIO_SHM_DATA_UNALIGNED 0x166
53 #define B43legacy_MMIO_XMITSTAT_0 0x170
54 #define B43legacy_MMIO_XMITSTAT_1 0x174
55 #define B43legacy_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
56 #define B43legacy_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
57 #define B43legacy_MMIO_TSF_CFP_REP 0x188
58 #define B43legacy_MMIO_TSF_CFP_START 0x18C
60 #define B43legacy_MMIO_DMA32_BASE0 0x200
61 #define B43legacy_MMIO_DMA32_BASE1 0x220
62 #define B43legacy_MMIO_DMA32_BASE2 0x240
63 #define B43legacy_MMIO_DMA32_BASE3 0x260
64 #define B43legacy_MMIO_DMA32_BASE4 0x280
65 #define B43legacy_MMIO_DMA32_BASE5 0x2A0
67 #define B43legacy_MMIO_DMA64_BASE0 0x200
68 #define B43legacy_MMIO_DMA64_BASE1 0x240
69 #define B43legacy_MMIO_DMA64_BASE2 0x280
70 #define B43legacy_MMIO_DMA64_BASE3 0x2C0
71 #define B43legacy_MMIO_DMA64_BASE4 0x300
72 #define B43legacy_MMIO_DMA64_BASE5 0x340
74 #define B43legacy_MMIO_PIO1_BASE 0x300
75 #define B43legacy_MMIO_PIO2_BASE 0x310
76 #define B43legacy_MMIO_PIO3_BASE 0x320
77 #define B43legacy_MMIO_PIO4_BASE 0x330
79 #define B43legacy_MMIO_PHY_VER 0x3E0
80 #define B43legacy_MMIO_PHY_RADIO 0x3E2
81 #define B43legacy_MMIO_PHY0 0x3E6
82 #define B43legacy_MMIO_ANTENNA 0x3E8
83 #define B43legacy_MMIO_CHANNEL 0x3F0
84 #define B43legacy_MMIO_CHANNEL_EXT 0x3F4
85 #define B43legacy_MMIO_RADIO_CONTROL 0x3F6
86 #define B43legacy_MMIO_RADIO_DATA_HIGH 0x3F8
87 #define B43legacy_MMIO_RADIO_DATA_LOW 0x3FA
88 #define B43legacy_MMIO_PHY_CONTROL 0x3FC
89 #define B43legacy_MMIO_PHY_DATA 0x3FE
90 #define B43legacy_MMIO_MACFILTER_CONTROL 0x420
91 #define B43legacy_MMIO_MACFILTER_DATA 0x422
92 #define B43legacy_MMIO_RCMTA_COUNT 0x43C /* Receive Match Transmitter Addr */
93 #define B43legacy_MMIO_RADIO_HWENABLED_LO 0x49A
94 #define B43legacy_MMIO_GPIO_CONTROL 0x49C
95 #define B43legacy_MMIO_GPIO_MASK 0x49E
96 #define B43legacy_MMIO_TSF_CFP_PRETBTT 0x612
97 #define B43legacy_MMIO_TSF_0 0x632 /* core rev < 3 only */
98 #define B43legacy_MMIO_TSF_1 0x634 /* core rev < 3 only */
99 #define B43legacy_MMIO_TSF_2 0x636 /* core rev < 3 only */
100 #define B43legacy_MMIO_TSF_3 0x638 /* core rev < 3 only */
101 #define B43legacy_MMIO_RNG 0x65A
102 #define B43legacy_MMIO_POWERUP_DELAY 0x6A8
105 #define B43legacy_BFL_PACTRL 0x0002
106 #define B43legacy_BFL_RSSI 0x0008
107 #define B43legacy_BFL_EXTLNA 0x1000
110 #define B43legacy_GPIO_CONTROL 0x6c
113 #define B43legacy_SHM_SHARED 0x0001
114 #define B43legacy_SHM_WIRELESS 0x0002
115 #define B43legacy_SHM_HW 0x0004
116 #define B43legacy_SHM_UCODE 0x0300
119 #define B43legacy_SHM_AUTOINC_R 0x0200 /* Read Auto-increment */
120 #define B43legacy_SHM_AUTOINC_W 0x0100 /* Write Auto-increment */
125 #define B43legacy_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */
126 #define B43legacy_SHM_SH_HOSTFLO 0x005E /* Hostflags ucode opts (low) */
127 #define B43legacy_SHM_SH_HOSTFHI 0x0060 /* Hostflags ucode opts (high) */
129 #define B43legacy_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block */
131 #define B43legacy_SHM_SH_DTIMP 0x0012 /* DTIM period */
132 #define B43legacy_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */
133 #define B43legacy_SHM_SH_BTL1 0x001A /* Beacon template length 1 */
134 #define B43legacy_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */
135 #define B43legacy_SHM_SH_TIMPOS 0x001E /* TIM position in beacon */
136 #define B43legacy_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word */
138 #define B43legacy_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word */
140 #define B43legacy_SHM_SH_PRTLEN 0x004A /* Probe Response template length */
141 #define B43legacy_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */
142 #define B43legacy_SHM_SH_PRPHYCTL 0x0188 /* Probe Resp PHY TX control */
144 #define B43legacy_SHM_SH_OFDMDIRECT 0x0480 /* Pointer to OFDM direct map */
145 #define B43legacy_SHM_SH_OFDMBASIC 0x04A0 /* Pointer to OFDM basic rate map */
146 #define B43legacy_SHM_SH_CCKDIRECT 0x04C0 /* Pointer to CCK direct map */
147 #define B43legacy_SHM_SH_CCKBASIC 0x04E0 /* Pointer to CCK basic rate map */
149 #define B43legacy_SHM_SH_UCODEREV 0x0000 /* Microcode revision */
150 #define B43legacy_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */
151 #define B43legacy_SHM_SH_UCODEDATE 0x0004 /* Microcode date */
152 #define B43legacy_SHM_SH_UCODETIME 0x0006 /* Microcode time */
153 #define B43legacy_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
154 #define B43legacy_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */
156 #define B43legacy_UCODEFLAGS_OFFSET 0x005E
163 #define B43legacy_HF_SYMW 0x00000002 /* G-PHY SYM workaround */
164 #define B43legacy_HF_GDCW 0x00000020 /* G-PHY DV cancel filter */
165 #define B43legacy_HF_OFDMPABOOST 0x00000040 /* Enable PA boost OFDM */
166 #define B43legacy_HF_EDCF 0x00000100 /* on if WME/MAC suspended */
169 #define B43legacy_MACFILTER_SELF 0x0000
170 #define B43legacy_MACFILTER_BSSID 0x0003
171 #define B43legacy_MACFILTER_MAC 0x0010
174 #define B43legacy_PHYTYPE_B 0x01
175 #define B43legacy_PHYTYPE_G 0x02
178 #define B43legacy_PHY_G_LO_CONTROL 0x0810
179 #define B43legacy_PHY_ILT_G_CTRL 0x0472
180 #define B43legacy_PHY_ILT_G_DATA1 0x0473
181 #define B43legacy_PHY_ILT_G_DATA2 0x0474
182 #define B43legacy_PHY_G_PCTL 0x0029
183 #define B43legacy_PHY_RADIO_BITFIELD 0x0401
184 #define B43legacy_PHY_G_CRS 0x0429
185 #define B43legacy_PHY_NRSSILT_CTRL 0x0803
186 #define B43legacy_PHY_NRSSILT_DATA 0x0804
189 #define B43legacy_RADIOCTL_ID 0x01
192 #define B43legacy_MACCTL_ENABLED 0x00000001 /* MAC Enabled */
193 #define B43legacy_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */
194 #define B43legacy_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */
195 #define B43legacy_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */
196 #define B43legacy_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */
197 #define B43legacy_MACCTL_BE 0x00010000 /* Big Endian mode */
198 #define B43legacy_MACCTL_INFRA 0x00020000 /* Infrastructure mode */
199 #define B43legacy_MACCTL_AP 0x00040000 /* AccessPoint mode */
200 #define B43legacy_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */
201 #define B43legacy_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */
202 #define B43legacy_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep bad PLCP frames */
203 #define B43legacy_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */
204 #define B43legacy_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */
205 #define B43legacy_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */
206 #define B43legacy_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */
207 #define B43legacy_MACCTL_AWAKE 0x04000000 /* Device is awake */
208 #define B43legacy_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */
209 #define B43legacy_MACCTL_GMODE 0x80000000 /* G Mode */
212 #define B43legacy_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */
213 #define B43legacy_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */
214 #define B43legacy_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */
215 #define B43legacy_MACCMD_CCA 0x00000008 /* Clear channel assessment */
216 #define B43legacy_MACCMD_BGNOISE 0x00000010 /* Background noise */
219 #define B43legacy_TMSLOW_GMODE 0x20000000 /* G Mode Enable */
220 #define B43legacy_TMSLOW_PLLREFSEL 0x00200000 /* PLL Freq Ref Select */
221 #define B43legacy_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Ctrl Enbl */
222 #define B43legacy_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */
223 #define B43legacy_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */
226 #define B43legacy_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available */
227 #define B43legacy_TMSHIGH_GPHY 0x00010000 /* G-PHY avail (rev >= 5) */
229 #define B43legacy_UCODEFLAG_AUTODIV 0x0001
232 #define B43legacy_IRQ_MAC_SUSPENDED 0x00000001
233 #define B43legacy_IRQ_BEACON 0x00000002
234 #define B43legacy_IRQ_TBTT_INDI 0x00000004 /* Target Beacon Transmit Time */
235 #define B43legacy_IRQ_BEACON_TX_OK 0x00000008
236 #define B43legacy_IRQ_BEACON_CANCEL 0x00000010
237 #define B43legacy_IRQ_ATIM_END 0x00000020
238 #define B43legacy_IRQ_PMQ 0x00000040
239 #define B43legacy_IRQ_PIO_WORKAROUND 0x00000100
240 #define B43legacy_IRQ_MAC_TXERR 0x00000200
241 #define B43legacy_IRQ_PHY_TXERR 0x00000800
242 #define B43legacy_IRQ_PMEVENT 0x00001000
243 #define B43legacy_IRQ_TIMER0 0x00002000
244 #define B43legacy_IRQ_TIMER1 0x00004000
245 #define B43legacy_IRQ_DMA 0x00008000
246 #define B43legacy_IRQ_TXFIFO_FLUSH_OK 0x00010000
247 #define B43legacy_IRQ_CCA_MEASURE_OK 0x00020000
248 #define B43legacy_IRQ_NOISESAMPLE_OK 0x00040000
249 #define B43legacy_IRQ_UCODE_DEBUG 0x08000000
250 #define B43legacy_IRQ_RFKILL 0x10000000
251 #define B43legacy_IRQ_TX_OK 0x20000000
252 #define B43legacy_IRQ_PHY_G_CHANGED 0x40000000
253 #define B43legacy_IRQ_TIMEOUT 0x80000000
255 #define B43legacy_IRQ_ALL 0xFFFFFFFF
297 B43legacy_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
306 #define B43legacy_CIR_BASE 0xf00
307 #define B43legacy_CIR_SBTPSFLAG (B43legacy_CIR_BASE + 0x18)
308 #define B43legacy_CIR_SBIMSTATE (B43legacy_CIR_BASE + 0x90)
309 #define B43legacy_CIR_SBINTVEC (B43legacy_CIR_BASE + 0x94)
310 #define B43legacy_CIR_SBTMSTATELOW (B43legacy_CIR_BASE + 0x98)
311 #define B43legacy_CIR_SBTMSTATEHIGH (B43legacy_CIR_BASE + 0x9c)
312 #define B43legacy_CIR_SBIMCONFIGLOW (B43legacy_CIR_BASE + 0xa8)
313 #define B43legacy_CIR_SB_ID_HI (B43legacy_CIR_BASE + 0xfc)
316 #define B43legacy_SBTMSTATEHIGH_SERROR 0x00000001
317 #define B43legacy_SBTMSTATEHIGH_BUSY 0x00000004
318 #define B43legacy_SBTMSTATEHIGH_TIMEOUT 0x00000020
319 #define B43legacy_SBTMSTATEHIGH_G_PHY_AVAIL 0x00010000
320 #define B43legacy_SBTMSTATEHIGH_COREFLAGS 0x1FFF0000
321 #define B43legacy_SBTMSTATEHIGH_DMA64BIT 0x10000000
322 #define B43legacy_SBTMSTATEHIGH_GATEDCLK 0x20000000
323 #define B43legacy_SBTMSTATEHIGH_BISTFAILED 0x40000000
324 #define B43legacy_SBTMSTATEHIGH_BISTCOMPLETE 0x80000000
327 #define B43legacy_SBIMSTATE_IB_ERROR 0x20000
328 #define B43legacy_SBIMSTATE_TIMEOUT 0x40000
343 } while (0)
349 # define B43legacy_BUG_ON(x) do { /* nothing */ } while (0)
350 # define B43legacy_DEBUG 0
375 #define B43legacy_IV_OFFSET_MASK 0x7FFF
376 #define B43legacy_IV_32BIT 0x8000
489 * bit 0-11: offset
492 * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
659 B43legacy_STAT_UNINIT = 0, /* Uninitialized. */
667 } while (0)
719 /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
772 return 0; in b43legacy_using_pio()
852 # define b43legacydbg(wl, fmt...) do { /* nothing */ } while (0)