Lines Matching +full:0 +full:x841
22 HT_RSSI_W1 = 0,
42 b43_radio_write(dev, 0x16, e->radio_syn16); in b43_radio_2059_channel_setup()
43 b43_radio_write(dev, 0x17, e->radio_syn17); in b43_radio_2059_channel_setup()
44 b43_radio_write(dev, 0x22, e->radio_syn22); in b43_radio_2059_channel_setup()
45 b43_radio_write(dev, 0x25, e->radio_syn25); in b43_radio_2059_channel_setup()
46 b43_radio_write(dev, 0x27, e->radio_syn27); in b43_radio_2059_channel_setup()
47 b43_radio_write(dev, 0x28, e->radio_syn28); in b43_radio_2059_channel_setup()
48 b43_radio_write(dev, 0x29, e->radio_syn29); in b43_radio_2059_channel_setup()
49 b43_radio_write(dev, 0x2c, e->radio_syn2c); in b43_radio_2059_channel_setup()
50 b43_radio_write(dev, 0x2d, e->radio_syn2d); in b43_radio_2059_channel_setup()
51 b43_radio_write(dev, 0x37, e->radio_syn37); in b43_radio_2059_channel_setup()
52 b43_radio_write(dev, 0x41, e->radio_syn41); in b43_radio_2059_channel_setup()
53 b43_radio_write(dev, 0x43, e->radio_syn43); in b43_radio_2059_channel_setup()
54 b43_radio_write(dev, 0x47, e->radio_syn47); in b43_radio_2059_channel_setup()
56 for (core = 0; core < 3; core++) { in b43_radio_2059_channel_setup()
58 b43_radio_write(dev, r | 0x4a, e->radio_rxtx4a); in b43_radio_2059_channel_setup()
59 b43_radio_write(dev, r | 0x58, e->radio_rxtx58); in b43_radio_2059_channel_setup()
60 b43_radio_write(dev, r | 0x5a, e->radio_rxtx5a); in b43_radio_2059_channel_setup()
61 b43_radio_write(dev, r | 0x6a, e->radio_rxtx6a); in b43_radio_2059_channel_setup()
62 b43_radio_write(dev, r | 0x6d, e->radio_rxtx6d); in b43_radio_2059_channel_setup()
63 b43_radio_write(dev, r | 0x6e, e->radio_rxtx6e); in b43_radio_2059_channel_setup()
64 b43_radio_write(dev, r | 0x92, e->radio_rxtx92); in b43_radio_2059_channel_setup()
65 b43_radio_write(dev, r | 0x98, e->radio_rxtx98); in b43_radio_2059_channel_setup()
71 b43_radio_mask(dev, R2059_RFPLL_MISC_EN, ~0x1); in b43_radio_2059_channel_setup()
72 b43_radio_mask(dev, R2059_RFPLL_MISC_CAL_RESETN, ~0x4); in b43_radio_2059_channel_setup()
73 b43_radio_set(dev, R2059_RFPLL_MISC_CAL_RESETN, 0x4); in b43_radio_2059_channel_setup()
74 b43_radio_set(dev, R2059_RFPLL_MISC_EN, 0x1); in b43_radio_2059_channel_setup()
83 b43_radio_set(dev, R2059_C3 | R2059_RCAL_CONFIG, 0x1); in b43_radio_2059_rcal()
86 b43_radio_set(dev, R2059_C3 | 0x0BF, 0x1); in b43_radio_2059_rcal()
87 b43_radio_maskset(dev, R2059_C3 | 0x19B, 0x3, 0x2); in b43_radio_2059_rcal()
90 b43_radio_set(dev, R2059_C3 | R2059_RCAL_CONFIG, 0x2); in b43_radio_2059_rcal()
94 b43_radio_mask(dev, R2059_C3 | R2059_RCAL_CONFIG, ~0x2); in b43_radio_2059_rcal()
98 b43err(dev->wl, "Radio 0x2059 rcal timeout\n"); in b43_radio_2059_rcal()
101 b43_radio_mask(dev, R2059_C3 | R2059_RCAL_CONFIG, ~0x1); in b43_radio_2059_rcal()
103 b43_radio_set(dev, 0xa, 0x60); in b43_radio_2059_rcal()
110 { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 }, in b43_radio_2057_rccal()
114 for (i = 0; i < 3; i++) { in b43_radio_2057_rccal()
115 b43_radio_write(dev, R2059_RCCAL_MASTER, radio_values[i][0]); in b43_radio_2057_rccal()
116 b43_radio_write(dev, R2059_RCCAL_X1, 0x6E); in b43_radio_2057_rccal()
120 b43_radio_write(dev, R2059_RCCAL_START_R1_Q1_P1, 0x55); in b43_radio_2057_rccal()
125 b43err(dev->wl, "Radio 0x2059 rccal timeout\n"); in b43_radio_2057_rccal()
128 b43_radio_write(dev, R2059_RCCAL_START_R1_Q1_P1, 0x15); in b43_radio_2057_rccal()
131 b43_radio_mask(dev, R2059_RCCAL_MASTER, ~0x1); in b43_radio_2057_rccal()
152 for (i = 0; i < ARRAY_SIZE(routing); i++) in b43_radio_2059_init()
153 b43_radio_set(dev, routing[i] | 0x146, 0x3); in b43_radio_2059_init()
157 b43_radio_set(dev, R2059_RFPLL_MISC_CAL_RESETN, 0x0078); in b43_radio_2059_init()
158 b43_radio_set(dev, R2059_XTAL_CONFIG2, 0x0080); in b43_radio_2059_init()
160 b43_radio_mask(dev, R2059_RFPLL_MISC_CAL_RESETN, ~0x0078); in b43_radio_2059_init()
161 b43_radio_mask(dev, R2059_XTAL_CONFIG2, ~0x0080); in b43_radio_2059_init()
168 b43_radio_mask(dev, R2059_RFPLL_MASTER, ~0x0008); in b43_radio_2059_init()
180 b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE, 0x3); in b43_phy_ht_force_rf_sequence()
183 for (i = 0; i < 200; i++) { in b43_phy_ht_force_rf_sequence()
185 i = 0; in b43_phy_ht_force_rf_sequence()
205 for (i = 0; i < 3; i++) in b43_phy_ht_pa_override()
208 for (i = 0; i < 3; i++) in b43_phy_ht_pa_override()
210 /* TODO: Does 5GHz band use different value (not 0x0400)? */ in b43_phy_ht_pa_override()
211 for (i = 0; i < 3; i++) in b43_phy_ht_pa_override()
212 b43_phy_write(dev, regs[i], 0x0400); in b43_phy_ht_pa_override()
253 static const u16 base[] = { 0x40, 0x60, 0x80 }; in b43_phy_ht_zero_extg()
255 for (i = 0; i < ARRAY_SIZE(base); i++) { in b43_phy_ht_zero_extg()
256 for (j = 0; j < 4; j++) in b43_phy_ht_zero_extg()
257 b43_phy_write(dev, B43_PHY_EXTG(base[i] + j), 0); in b43_phy_ht_zero_extg()
260 for (i = 0; i < ARRAY_SIZE(base); i++) in b43_phy_ht_zero_extg()
261 b43_phy_write(dev, B43_PHY_EXTG(base[i] + 0xc), 0); in b43_phy_ht_zero_extg()
275 for (i = 0; i < 3; i++) { in b43_phy_ht_afe_unk1()
277 b43_phy_set(dev, ctl_regs[i][1], 0x4); in b43_phy_ht_afe_unk1()
278 b43_phy_set(dev, ctl_regs[i][0], 0x4); in b43_phy_ht_afe_unk1()
279 b43_phy_mask(dev, ctl_regs[i][1], ~0x1); in b43_phy_ht_afe_unk1()
280 b43_phy_set(dev, ctl_regs[i][0], 0x1); in b43_phy_ht_afe_unk1()
281 b43_httab_write(dev, B43_HTTAB16(8, 5 + (i * 0x10)), 0); in b43_phy_ht_afe_unk1()
282 b43_phy_mask(dev, ctl_regs[i][0], ~0x4); in b43_phy_ht_afe_unk1()
288 clip_st[0] = b43_phy_read(dev, B43_PHY_HT_C1_CLIP1THRES); in b43_phy_ht_read_clip_detection()
298 val = 0x1E1F; in b43_phy_ht_bphy_init()
299 for (i = 0; i < 16; i++) { in b43_phy_ht_bphy_init()
300 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val); in b43_phy_ht_bphy_init()
301 val -= 0x202; in b43_phy_ht_bphy_init()
303 val = 0x3E3F; in b43_phy_ht_bphy_init()
304 for (i = 0; i < 16; i++) { in b43_phy_ht_bphy_init()
305 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val); in b43_phy_ht_bphy_init()
306 val -= 0x202; in b43_phy_ht_bphy_init()
308 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668); in b43_phy_ht_bphy_init()
325 0xffff & ~(B43_PHY_B_BBCFG_RSTCCA | in b43_phy_ht_bphy_reset()
342 if (tmp & 0x1) in b43_phy_ht_stop_playback()
344 else if (tmp & 0x2) in b43_phy_ht_stop_playback()
345 b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, 0x7FFF); in b43_phy_ht_stop_playback()
347 b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0x0004); in b43_phy_ht_stop_playback()
349 for (i = 0; i < 3; i++) { in b43_phy_ht_stop_playback()
350 if (phy_ht->bb_mult_save[i] >= 0) { in b43_phy_ht_stop_playback()
351 b43_httab_write(dev, B43_HTTAB16(13, 0x63 + i * 4), in b43_phy_ht_stop_playback()
353 b43_httab_write(dev, B43_HTTAB16(13, 0x67 + i * 4), in b43_phy_ht_stop_playback()
364 b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, 0x4400); in b43_phy_ht_load_samples()
366 for (i = 0; i < len; i++) { in b43_phy_ht_load_samples()
367 b43_phy_write(dev, B43_PHY_HT_TABLE_DATAHI, 0); in b43_phy_ht_load_samples()
368 b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, 0); in b43_phy_ht_load_samples()
381 for (i = 0; i < 3; i++) { in b43_phy_ht_run_samples()
382 if (phy_ht->bb_mult_save[i] < 0) in b43_phy_ht_run_samples()
383 phy_ht->bb_mult_save[i] = b43_httab_read(dev, B43_HTTAB16(13, 0x63 + i * 4)); in b43_phy_ht_run_samples()
387 if (loops != 0xFFFF) in b43_phy_ht_run_samples()
397 b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0); in b43_phy_ht_run_samples()
398 b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0); in b43_phy_ht_run_samples()
399 b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, ~0); in b43_phy_ht_run_samples()
400 b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, 0x1); in b43_phy_ht_run_samples()
402 for (i = 0; i < 100; i++) { in b43_phy_ht_run_samples()
404 i = 0; in b43_phy_ht_run_samples()
420 b43_phy_ht_run_samples(dev, samp, 0xFFFF, 0); in b43_phy_ht_tx_tone()
438 if (core_sel == 0) { in b43_phy_ht_rssi_select()
441 for (core = 0; core < 3; core++) { in b43_phy_ht_rssi_select()
443 if ((core_sel == 1 && core != 0) || in b43_phy_ht_rssi_select()
450 b43_phy_set(dev, ctl_regs[core][0], 0x3 << 8); in b43_phy_ht_rssi_select()
451 b43_phy_set(dev, ctl_regs[core][0], 0x3 << 10); in b43_phy_ht_rssi_select()
452 b43_phy_set(dev, ctl_regs[core][1], 0x1 << 9); in b43_phy_ht_rssi_select()
453 b43_phy_set(dev, ctl_regs[core][1], 0x1 << 10); in b43_phy_ht_rssi_select()
455 b43_radio_set(dev, R2059_C3 | 0xbf, 0x1); in b43_phy_ht_rssi_select()
456 b43_radio_write(dev, radio_r[core] | 0x159, in b43_phy_ht_rssi_select()
457 0x11); in b43_phy_ht_rssi_select()
473 0x848, 0x841, in b43_phy_ht_poll_rssi()
475 0x868, 0x861, in b43_phy_ht_poll_rssi()
477 0x888, 0x881, in b43_phy_ht_poll_rssi()
482 for (i = 0; i < 12; i++) in b43_phy_ht_poll_rssi()
487 for (i = 0; i < 6; i++) in b43_phy_ht_poll_rssi()
488 buf[i] = 0; in b43_phy_ht_poll_rssi()
490 for (i = 0; i < nsamp; i++) { in b43_phy_ht_poll_rssi()
491 tmp[0] = b43_phy_read(dev, B43_PHY_HT_RSSI_C1); in b43_phy_ht_poll_rssi()
495 buf[0] += ((s8)((tmp[0] & 0x3F) << 2)) >> 2; in b43_phy_ht_poll_rssi()
496 buf[1] += ((s8)(((tmp[0] >> 8) & 0x3F) << 2)) >> 2; in b43_phy_ht_poll_rssi()
497 buf[2] += ((s8)((tmp[1] & 0x3F) << 2)) >> 2; in b43_phy_ht_poll_rssi()
498 buf[3] += ((s8)(((tmp[1] >> 8) & 0x3F) << 2)) >> 2; in b43_phy_ht_poll_rssi()
499 buf[4] += ((s8)((tmp[2] & 0x3F) << 2)) >> 2; in b43_phy_ht_poll_rssi()
500 buf[5] += ((s8)(((tmp[2] >> 8) & 0x3F) << 2)) >> 2; in b43_phy_ht_poll_rssi()
503 for (i = 0; i < 12; i++) in b43_phy_ht_poll_rssi()
515 for (i = 0; i < 3; i++) { in b43_phy_ht_tx_power_fix()
517 u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8)); in b43_phy_ht_tx_power_fix()
519 if (0) /* FIXME */ in b43_phy_ht_tx_power_fix()
520 mask = 0x2 << (i * 4); in b43_phy_ht_tx_power_fix()
522 mask = 0; in b43_phy_ht_tx_power_fix()
523 b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask); in b43_phy_ht_tx_power_fix()
525 b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16); in b43_phy_ht_tx_power_fix()
526 b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)), in b43_phy_ht_tx_power_fix()
527 tmp & 0xFF); in b43_phy_ht_tx_power_fix()
528 b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)), in b43_phy_ht_tx_power_fix()
529 tmp & 0xFF); in b43_phy_ht_tx_power_fix()
550 for (i = 0; i < 3; i++) in b43_phy_ht_tx_power_ctl()
554 b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0xffff & ~en_bits); in b43_phy_ht_tx_power_ctl()
559 for (i = 0; i < 3; i++) in b43_phy_ht_tx_power_ctl()
560 b43_phy_write(dev, cmd_regs[i], 0x32); in b43_phy_ht_tx_power_ctl()
563 for (i = 0; i < 3; i++) in b43_phy_ht_tx_power_ctl()
576 static const u16 base[] = { 0x840, 0x860, 0x880 }; in b43_phy_ht_tx_power_ctl_idle_tssi()
581 for (core = 0; core < 3; core++) { in b43_phy_ht_tx_power_ctl_idle_tssi()
584 save_regs[core][0] = b43_phy_read(dev, base[core] + 0); in b43_phy_ht_tx_power_ctl_idle_tssi()
586 b43_phy_write(dev, base[core] + 6, 0); in b43_phy_ht_tx_power_ctl_idle_tssi()
587 b43_phy_mask(dev, base[core] + 7, ~0xF); /* 0xF? Or just 0x6? */ in b43_phy_ht_tx_power_ctl_idle_tssi()
588 b43_phy_set(dev, base[core] + 0, 0x0400); in b43_phy_ht_tx_power_ctl_idle_tssi()
589 b43_phy_set(dev, base[core] + 0, 0x1000); in b43_phy_ht_tx_power_ctl_idle_tssi()
598 phy_ht->idle_tssi[0] = rssi_buf[0] & 0xff; in b43_phy_ht_tx_power_ctl_idle_tssi()
599 phy_ht->idle_tssi[1] = rssi_buf[2] & 0xff; in b43_phy_ht_tx_power_ctl_idle_tssi()
600 phy_ht->idle_tssi[2] = rssi_buf[4] & 0xff; in b43_phy_ht_tx_power_ctl_idle_tssi()
602 for (core = 0; core < 3; core++) { in b43_phy_ht_tx_power_ctl_idle_tssi()
603 b43_phy_write(dev, base[core] + 0, save_regs[core][0]); in b43_phy_ht_tx_power_ctl_idle_tssi()
614 /* 0x159 is probably TX_SSI_MUX or TSSIG (by comparing to N-PHY) */ in b43_phy_ht_tssi_setup()
615 for (core = 0; core < 3; core++) { in b43_phy_ht_tssi_setup()
616 b43_radio_set(dev, 0x8bf, 0x1); in b43_phy_ht_tssi_setup()
617 b43_radio_write(dev, routing[core] | 0x0159, 0x0011); in b43_phy_ht_tssi_setup()
634 for (c = 0; c < 3; c++) { in b43_phy_ht_tx_power_ctl_setup()
636 a1[c] = sprom->core_pwr_info[c].pa_2g[0]; in b43_phy_ht_tx_power_ctl_setup()
641 for (c = 0; c < 3; c++) { in b43_phy_ht_tx_power_ctl_setup()
643 a1[c] = sprom->core_pwr_info[c].pa_5gl[0]; in b43_phy_ht_tx_power_ctl_setup()
648 for (c = 0; c < 3; c++) { in b43_phy_ht_tx_power_ctl_setup()
650 a1[c] = sprom->core_pwr_info[c].pa_5g[0]; in b43_phy_ht_tx_power_ctl_setup()
655 for (c = 0; c < 3; c++) { in b43_phy_ht_tx_power_ctl_setup()
657 a1[c] = sprom->core_pwr_info[c].pa_5gh[0]; in b43_phy_ht_tx_power_ctl_setup()
662 target[0] = target[1] = target[2] = 52; in b43_phy_ht_tx_power_ctl_setup()
663 a1[0] = a1[1] = a1[2] = -424; in b43_phy_ht_tx_power_ctl_setup()
664 b0[0] = b0[1] = b0[2] = 5612; in b43_phy_ht_tx_power_ctl_setup()
665 b1[0] = b1[1] = b1[2] = -1393; in b43_phy_ht_tx_power_ctl_setup()
670 ~B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN & 0xFFFF); in b43_phy_ht_tx_power_ctl_setup()
673 b43_phy_set(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI, 0x4000); in b43_phy_ht_tx_power_ctl_setup()
676 ~B43_PHY_HT_TXPCTL_CMD_C1_INIT, 0x19); in b43_phy_ht_tx_power_ctl_setup()
678 ~B43_PHY_HT_TXPCTL_CMD_C2_INIT, 0x19); in b43_phy_ht_tx_power_ctl_setup()
680 ~B43_PHY_HT_TXPCTL_CMD_C3_INIT, 0x19); in b43_phy_ht_tx_power_ctl_setup()
687 idle[0] << B43_PHY_HT_TXPCTL_IDLE_TSSI_C1_SHIFT); in b43_phy_ht_tx_power_ctl_setup()
696 0xf0); in b43_phy_ht_tx_power_ctl_setup()
698 0x3 << B43_PHY_HT_TXPCTL_N_NPTIL2_SHIFT); in b43_phy_ht_tx_power_ctl_setup()
699 #if 0 in b43_phy_ht_tx_power_ctl_setup()
701 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0x800, 0) in b43_phy_ht_tx_power_ctl_setup()
702 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0x400, 0) in b43_phy_ht_tx_power_ctl_setup()
707 target[0] << B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT); in b43_phy_ht_tx_power_ctl_setup()
709 ~B43_PHY_HT_TXPCTL_TARG_PWR_C2 & 0xFFFF, in b43_phy_ht_tx_power_ctl_setup()
715 for (c = 0; c < 3; c++) { in b43_phy_ht_tx_power_ctl_setup()
719 for (i = 0; i < 64; i++) { in b43_phy_ht_tx_power_ctl_setup()
725 b43_httab_write_bulk(dev, B43_HTTAB16(26 + c, 0), 64, regval); in b43_phy_ht_tx_power_ctl_setup()
737 int spuravoid = 0; in b43_phy_ht_spur_avoid()
742 bcma_core_pll_ctl(core, B43_BCMA_CLKCTLST_PHY_PLL_REQ, 0, false); in b43_phy_ht_spur_avoid()
758 ~B43_PHY_HT_BBCFG_RSTRX & 0xFFFF); in b43_phy_ht_spur_avoid()
790 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN, 0); in b43_phy_ht_channel_setup()
791 b43_phy_set(dev, B43_PHY_HT_TEST, 0x0800); in b43_phy_ht_channel_setup()
796 b43_phy_mask(dev, B43_PHY_HT_TEST, ~0x840); in b43_phy_ht_channel_setup()
804 b43_phy_write(dev, 0x017e, 0x3830); in b43_phy_ht_channel_setup()
815 if (phy->radio_ver == 0x2059) { in b43_phy_ht_set_channel()
826 if (phy->radio_ver == 0x2059) { in b43_phy_ht_set_channel()
834 return 0; in b43_phy_ht_set_channel()
850 return 0; in b43_phy_ht_op_allocate()
859 memset(phy_ht, 0, sizeof(*phy_ht)); in b43_phy_ht_op_prepare_structs()
862 for (i = 0; i < 3; i++) in b43_phy_ht_op_prepare_structs()
865 for (i = 0; i < 3; i++) in b43_phy_ht_op_prepare_structs()
883 b43_phy_mask(dev, 0x0be, ~0x2); in b43_phy_ht_op_init()
884 b43_phy_set(dev, 0x23f, 0x7ff); in b43_phy_ht_op_init()
885 b43_phy_set(dev, 0x240, 0x7ff); in b43_phy_ht_op_init()
886 b43_phy_set(dev, 0x241, 0x7ff); in b43_phy_ht_op_init()
890 b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3); in b43_phy_ht_op_init()
892 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0); in b43_phy_ht_op_init()
893 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0); in b43_phy_ht_op_init()
894 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0); in b43_phy_ht_op_init()
896 b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20); in b43_phy_ht_op_init()
897 b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20); in b43_phy_ht_op_init()
898 b43_phy_write(dev, 0x20d, 0xb8); in b43_phy_ht_op_init()
899 b43_phy_write(dev, B43_PHY_EXTG(0x14f), 0xc8); in b43_phy_ht_op_init()
900 b43_phy_write(dev, 0x70, 0x50); in b43_phy_ht_op_init()
901 b43_phy_write(dev, 0x1ff, 0x30); in b43_phy_ht_op_init()
904 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN, 0); in b43_phy_ht_op_init()
909 b43_phy_set(dev, 0xb1, 0x91); in b43_phy_ht_op_init()
910 b43_phy_write(dev, 0x32f, 0x0003); in b43_phy_ht_op_init()
911 b43_phy_write(dev, 0x077, 0x0010); in b43_phy_ht_op_init()
912 b43_phy_write(dev, 0x0b4, 0x0258); in b43_phy_ht_op_init()
913 b43_phy_mask(dev, 0x17e, ~0x4000); in b43_phy_ht_op_init()
915 b43_phy_write(dev, 0x0b9, 0x0072); in b43_phy_ht_op_init()
917 b43_httab_write_few(dev, B43_HTTAB16(7, 0x14e), 2, 0x010f, 0x010f); in b43_phy_ht_op_init()
918 b43_httab_write_few(dev, B43_HTTAB16(7, 0x15e), 2, 0x010f, 0x010f); in b43_phy_ht_op_init()
919 b43_httab_write_few(dev, B43_HTTAB16(7, 0x16e), 2, 0x010f, 0x010f); in b43_phy_ht_op_init()
923 b43_httab_write_few(dev, B43_HTTAB16(7, 0x130), 9, 0x777, 0x111, 0x111, in b43_phy_ht_op_init()
924 0x777, 0x111, 0x111, 0x777, 0x111, 0x111); in b43_phy_ht_op_init()
926 b43_httab_write(dev, B43_HTTAB16(7, 0x120), 0x0777); in b43_phy_ht_op_init()
927 b43_httab_write(dev, B43_HTTAB16(7, 0x124), 0x0777); in b43_phy_ht_op_init()
929 b43_httab_write(dev, B43_HTTAB16(8, 0x00), 0x02); in b43_phy_ht_op_init()
930 b43_httab_write(dev, B43_HTTAB16(8, 0x10), 0x02); in b43_phy_ht_op_init()
931 b43_httab_write(dev, B43_HTTAB16(8, 0x20), 0x02); in b43_phy_ht_op_init()
933 b43_httab_write_few(dev, B43_HTTAB16(8, 0x08), 4, in b43_phy_ht_op_init()
934 0x8e, 0x96, 0x96, 0x96); in b43_phy_ht_op_init()
935 b43_httab_write_few(dev, B43_HTTAB16(8, 0x18), 4, in b43_phy_ht_op_init()
936 0x8f, 0x9f, 0x9f, 0x9f); in b43_phy_ht_op_init()
937 b43_httab_write_few(dev, B43_HTTAB16(8, 0x28), 4, in b43_phy_ht_op_init()
938 0x8f, 0x9f, 0x9f, 0x9f); in b43_phy_ht_op_init()
940 b43_httab_write_few(dev, B43_HTTAB16(8, 0x0c), 4, 0x2, 0x2, 0x2, 0x2); in b43_phy_ht_op_init()
941 b43_httab_write_few(dev, B43_HTTAB16(8, 0x1c), 4, 0x2, 0x2, 0x2, 0x2); in b43_phy_ht_op_init()
942 b43_httab_write_few(dev, B43_HTTAB16(8, 0x2c), 4, 0x2, 0x2, 0x2, 0x2); in b43_phy_ht_op_init()
944 b43_phy_maskset(dev, 0x0280, 0xff00, 0x3e); in b43_phy_ht_op_init()
945 b43_phy_maskset(dev, 0x0283, 0xff00, 0x3e); in b43_phy_ht_op_init()
946 b43_phy_maskset(dev, B43_PHY_OFDM(0x0141), 0xff00, 0x46); in b43_phy_ht_op_init()
947 b43_phy_maskset(dev, 0x0283, 0xff00, 0x40); in b43_phy_ht_op_init()
949 b43_httab_write_few(dev, B43_HTTAB16(00, 0x8), 4, in b43_phy_ht_op_init()
950 0x09, 0x0e, 0x13, 0x18); in b43_phy_ht_op_init()
951 b43_httab_write_few(dev, B43_HTTAB16(01, 0x8), 4, in b43_phy_ht_op_init()
952 0x09, 0x0e, 0x13, 0x18); in b43_phy_ht_op_init()
954 b43_httab_write_few(dev, B43_HTTAB16(40, 0x8), 4, in b43_phy_ht_op_init()
955 0x09, 0x0e, 0x13, 0x18); in b43_phy_ht_op_init()
957 b43_phy_maskset(dev, B43_PHY_OFDM(0x24), 0x3f, 0xd); in b43_phy_ht_op_init()
958 b43_phy_maskset(dev, B43_PHY_OFDM(0x64), 0x3f, 0xd); in b43_phy_ht_op_init()
959 b43_phy_maskset(dev, B43_PHY_OFDM(0xa4), 0x3f, 0xd); in b43_phy_ht_op_init()
961 b43_phy_set(dev, B43_PHY_EXTG(0x060), 0x1); in b43_phy_ht_op_init()
962 b43_phy_set(dev, B43_PHY_EXTG(0x064), 0x1); in b43_phy_ht_op_init()
963 b43_phy_set(dev, B43_PHY_EXTG(0x080), 0x1); in b43_phy_ht_op_init()
964 b43_phy_set(dev, B43_PHY_EXTG(0x084), 0x1); in b43_phy_ht_op_init()
967 tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x144)); in b43_phy_ht_op_init()
968 b43_httab_write(dev, B43_HTTAB16(7, 0x14a), tmp); in b43_phy_ht_op_init()
969 tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x154)); in b43_phy_ht_op_init()
970 b43_httab_write(dev, B43_HTTAB16(7, 0x15a), tmp); in b43_phy_ht_op_init()
971 tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x164)); in b43_phy_ht_op_init()
972 b43_httab_write(dev, B43_HTTAB16(7, 0x16a), tmp); in b43_phy_ht_op_init()
989 b43_phy_ht_classifier(dev, 0, 0); in b43_phy_ht_op_init()
995 b43_httab_write_bulk(dev, B43_HTTAB32(0x1a, 0xc0), in b43_phy_ht_op_init()
1006 return 0; in b43_phy_ht_op_init()
1029 if (dev->phy.radio_ver == 0x2059) in b43_phy_ht_op_software_rfkill()
1041 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00cd); in b43_phy_ht_op_switch_analog()
1042 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x0000); in b43_phy_ht_op_switch_analog()
1043 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00cd); in b43_phy_ht_op_switch_analog()
1044 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x0000); in b43_phy_ht_op_switch_analog()
1045 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00cd); in b43_phy_ht_op_switch_analog()
1046 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x0000); in b43_phy_ht_op_switch_analog()
1048 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x07ff); in b43_phy_ht_op_switch_analog()
1049 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00fd); in b43_phy_ht_op_switch_analog()
1050 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x07ff); in b43_phy_ht_op_switch_analog()
1051 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00fd); in b43_phy_ht_op_switch_analog()
1052 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x07ff); in b43_phy_ht_op_switch_analog()
1053 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00fd); in b43_phy_ht_op_switch_analog()
1095 /* HT-PHY needs 0x200 for read access */ in b43_phy_ht_op_radio_read()
1096 reg |= 0x200; in b43_phy_ht_op_radio_read()