Lines Matching +full:0 +full:x4321
78 "enable(1) / disable(0) Bad Frames Preemption");
106 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
110 MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
118 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
119 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x15, BCMA_ANY_CLASS),
120 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
121 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
122 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1C, BCMA_ANY_CLASS),
123 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
124 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1E, BCMA_ANY_CLASS),
125 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x28, BCMA_ANY_CLASS),
126 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x2A, BCMA_ANY_CLASS),
165 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
169 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
170 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
171 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
172 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
173 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
174 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
175 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
176 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
181 #define b43_b_ratetable (__b43_ratetable + 0)
183 #define b43_g_ratetable (__b43_ratetable + 0)
191 .max_antenna_gain = 0, \
195 CHAN2G(1, 2412, 0),
196 CHAN2G(2, 2417, 0),
197 CHAN2G(3, 2422, 0),
198 CHAN2G(4, 2427, 0),
199 CHAN2G(5, 2432, 0),
200 CHAN2G(6, 2437, 0),
201 CHAN2G(7, 2442, 0),
202 CHAN2G(8, 2447, 0),
203 CHAN2G(9, 2452, 0),
204 CHAN2G(10, 2457, 0),
205 CHAN2G(11, 2462, 0),
206 CHAN2G(12, 2467, 0),
207 CHAN2G(13, 2472, 0),
208 CHAN2G(14, 2484, 0),
220 .max_antenna_gain = 0, \
228 .max_antenna_gain = 0, \
232 CHAN4G(184, 0), CHAN4G(186, 0),
233 CHAN4G(188, 0), CHAN4G(190, 0),
234 CHAN4G(192, 0), CHAN4G(194, 0),
235 CHAN4G(196, 0), CHAN4G(198, 0),
236 CHAN4G(200, 0), CHAN4G(202, 0),
237 CHAN4G(204, 0), CHAN4G(206, 0),
238 CHAN4G(208, 0), CHAN4G(210, 0),
239 CHAN4G(212, 0), CHAN4G(214, 0),
240 CHAN4G(216, 0), CHAN4G(218, 0),
241 CHAN4G(220, 0), CHAN4G(222, 0),
242 CHAN4G(224, 0), CHAN4G(226, 0),
243 CHAN4G(228, 0),
244 CHAN5G(32, 0), CHAN5G(34, 0),
245 CHAN5G(36, 0), CHAN5G(38, 0),
246 CHAN5G(40, 0), CHAN5G(42, 0),
247 CHAN5G(44, 0), CHAN5G(46, 0),
248 CHAN5G(48, 0), CHAN5G(50, 0),
249 CHAN5G(52, 0), CHAN5G(54, 0),
250 CHAN5G(56, 0), CHAN5G(58, 0),
251 CHAN5G(60, 0), CHAN5G(62, 0),
252 CHAN5G(64, 0), CHAN5G(66, 0),
253 CHAN5G(68, 0), CHAN5G(70, 0),
254 CHAN5G(72, 0), CHAN5G(74, 0),
255 CHAN5G(76, 0), CHAN5G(78, 0),
256 CHAN5G(80, 0), CHAN5G(82, 0),
257 CHAN5G(84, 0), CHAN5G(86, 0),
258 CHAN5G(88, 0), CHAN5G(90, 0),
259 CHAN5G(92, 0), CHAN5G(94, 0),
260 CHAN5G(96, 0), CHAN5G(98, 0),
261 CHAN5G(100, 0), CHAN5G(102, 0),
262 CHAN5G(104, 0), CHAN5G(106, 0),
263 CHAN5G(108, 0), CHAN5G(110, 0),
264 CHAN5G(112, 0), CHAN5G(114, 0),
265 CHAN5G(116, 0), CHAN5G(118, 0),
266 CHAN5G(120, 0), CHAN5G(122, 0),
267 CHAN5G(124, 0), CHAN5G(126, 0),
268 CHAN5G(128, 0), CHAN5G(130, 0),
269 CHAN5G(132, 0), CHAN5G(134, 0),
270 CHAN5G(136, 0), CHAN5G(138, 0),
271 CHAN5G(140, 0), CHAN5G(142, 0),
272 CHAN5G(144, 0), CHAN5G(145, 0),
273 CHAN5G(146, 0), CHAN5G(147, 0),
274 CHAN5G(148, 0), CHAN5G(149, 0),
275 CHAN5G(150, 0), CHAN5G(151, 0),
276 CHAN5G(152, 0), CHAN5G(153, 0),
277 CHAN5G(154, 0), CHAN5G(155, 0),
278 CHAN5G(156, 0), CHAN5G(157, 0),
279 CHAN5G(158, 0), CHAN5G(159, 0),
280 CHAN5G(160, 0), CHAN5G(161, 0),
281 CHAN5G(162, 0), CHAN5G(163, 0),
282 CHAN5G(164, 0), CHAN5G(165, 0),
283 CHAN5G(166, 0), CHAN5G(168, 0),
284 CHAN5G(170, 0), CHAN5G(172, 0),
285 CHAN5G(174, 0), CHAN5G(176, 0),
286 CHAN5G(178, 0), CHAN5G(180, 0),
287 CHAN5G(182, 0),
291 CHAN5G(36, 0), CHAN5G(40, 0),
292 CHAN5G(44, 0), CHAN5G(48, 0),
293 CHAN5G(149, 0), CHAN5G(153, 0),
294 CHAN5G(157, 0), CHAN5G(161, 0),
295 CHAN5G(165, 0),
299 CHAN5G(34, 0), CHAN5G(36, 0),
300 CHAN5G(38, 0), CHAN5G(40, 0),
301 CHAN5G(42, 0), CHAN5G(44, 0),
302 CHAN5G(46, 0), CHAN5G(48, 0),
303 CHAN5G(52, 0), CHAN5G(56, 0),
304 CHAN5G(60, 0), CHAN5G(64, 0),
305 CHAN5G(100, 0), CHAN5G(104, 0),
306 CHAN5G(108, 0), CHAN5G(112, 0),
307 CHAN5G(116, 0), CHAN5G(120, 0),
308 CHAN5G(124, 0), CHAN5G(128, 0),
309 CHAN5G(132, 0), CHAN5G(136, 0),
310 CHAN5G(140, 0), CHAN5G(149, 0),
311 CHAN5G(153, 0), CHAN5G(157, 0),
312 CHAN5G(161, 0), CHAN5G(165, 0),
313 CHAN5G(184, 0), CHAN5G(188, 0),
314 CHAN5G(192, 0), CHAN5G(196, 0),
315 CHAN5G(200, 0), CHAN5G(204, 0),
316 CHAN5G(208, 0), CHAN5G(212, 0),
317 CHAN5G(216, 0),
468 B43_WARN_ON(offset % 4 != 0); in b43_ram_write()
495 B43_WARN_ON(offset & 0x0001); in b43_shm_read32()
496 if (offset & 0x0003) { in b43_shm_read32()
518 B43_WARN_ON(offset & 0x0001); in b43_shm_read16()
519 if (offset & 0x0003) { in b43_shm_read16()
537 B43_WARN_ON(offset & 0x0001); in b43_shm_write32()
538 if (offset & 0x0003) { in b43_shm_write32()
542 value & 0xFFFF); in b43_shm_write32()
545 (value >> 16) & 0xFFFF); in b43_shm_write32()
557 B43_WARN_ON(offset & 0x0001); in b43_shm_write16()
558 if (offset & 0x0003) { in b43_shm_write16()
589 lo = (value & 0x00000000FFFFULL); in b43_hf_write()
590 mi = (value & 0x0000FFFF0000ULL) >> 16; in b43_hf_write()
591 hi = (value & 0xFFFF00000000ULL) >> 32; in b43_hf_write()
622 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD); in b43_time_lock()
629 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0); in b43_time_unlock()
658 static const u8 zero_addr[ETH_ALEN] = { 0 }; in b43_macfilter_set()
664 offset |= 0x0020; in b43_macfilter_set()
667 data = mac[0]; in b43_macfilter_set()
695 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) { in b43_write_mac_bssid_templates()
696 tmp = (u32) (mac_bssid[i + 0]); in b43_write_mac_bssid_templates()
700 b43_ram_write(dev, 0x20 + i, tmp); in b43_write_mac_bssid_templates()
717 /* Shared memory location 0x0010 is the slot time and should be in b43_set_slot_time()
718 * set to slot_time; however, this register is initially 0 and changing in b43_set_slot_time()
722 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time); in b43_set_slot_time()
745 0x00000000, in b43_dummy_transmission()
746 0x00D40000, in b43_dummy_transmission()
747 0x00000000, in b43_dummy_transmission()
748 0x01000000, in b43_dummy_transmission()
749 0x00000000, in b43_dummy_transmission()
753 max_loop = 0x1E; in b43_dummy_transmission()
754 buffer[0] = 0x000201CC; in b43_dummy_transmission()
756 max_loop = 0xFA; in b43_dummy_transmission()
757 buffer[0] = 0x000B846E; in b43_dummy_transmission()
760 for (i = 0; i < 5; i++) in b43_dummy_transmission()
763 b43_write16(dev, B43_MMIO_XMTSEL, 0x0000); in b43_dummy_transmission()
766 b43_write16(dev, B43_MMIO_WEPCTL, 0x0000); in b43_dummy_transmission()
768 b43_write16(dev, B43_MMIO_WEPCTL, 0x0100); in b43_dummy_transmission()
770 value = (ofdm ? 0x41 : 0x40); in b43_dummy_transmission()
774 b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02); in b43_dummy_transmission()
776 b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000); in b43_dummy_transmission()
777 b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000); in b43_dummy_transmission()
779 b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000); in b43_dummy_transmission()
780 b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014); in b43_dummy_transmission()
781 b43_write16(dev, B43_MMIO_XMTSEL, 0x0826); in b43_dummy_transmission()
782 b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000); in b43_dummy_transmission()
791 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0); in b43_dummy_transmission()
794 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050); in b43_dummy_transmission()
797 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030); in b43_dummy_transmission()
801 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) in b43_dummy_transmission()
802 b43_radio_write16(dev, 0x0051, 0x0017); in b43_dummy_transmission()
803 for (i = 0x00; i < max_loop; i++) { in b43_dummy_transmission()
805 if (value & 0x0080) in b43_dummy_transmission()
809 for (i = 0x00; i < 0x0A; i++) { in b43_dummy_transmission()
811 if (value & 0x0400) in b43_dummy_transmission()
815 for (i = 0x00; i < 0x19; i++) { in b43_dummy_transmission()
817 if (!(value & 0x0100)) in b43_dummy_transmission()
821 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) in b43_dummy_transmission()
822 b43_radio_write16(dev, 0x0051, 0x0037); in b43_dummy_transmission()
841 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { in key_write()
850 u32 addrtmp[2] = { 0, 0, }; in keymac_write()
858 * Physical mac 0 is mapped to physical key 4 or 8, depending in keymac_write()
866 addrtmp[0] = addr[0]; in keymac_write()
867 addrtmp[0] |= ((u32) (addr[1]) << 8); in keymac_write()
868 addrtmp[0] |= ((u32) (addr[2]) << 16); in keymac_write()
869 addrtmp[0] |= ((u32) (addr[3]) << 24); in keymac_write()
876 (index * 2) + 0, addrtmp[0]); in keymac_write()
913 * Physical mac 0 is mapped to physical key 4 or 8, depending in rx_tkip_phase1_write()
921 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n", in rx_tkip_phase1_write()
926 for (i = 0; i < 10; i += 2) { in rx_tkip_phase1_write()
928 phase1key ? phase1key[i / 2] : 0); in rx_tkip_phase1_write()
966 u8 buf[B43_SEC_KEYSIZE] = { 0, }; in do_key_write()
980 * We could start with iv32=0 and compute the corresponding in do_key_write()
984 * 0xffffffff and let's b43_op_update_tkip_key provide a in do_key_write()
987 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf); in do_key_write()
989 rx_tkip_phase1_write(dev, index, 0, NULL); in do_key_write()
1019 for (i = 0; i < ARRAY_SIZE(dev->key); i++) { in b43_key_write()
1023 if (index < 0) { in b43_key_write()
1039 if (index < 0) { in b43_key_write()
1055 return 0; in b43_key_write()
1060 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key)))) in b43_key_clear()
1070 return 0; in b43_key_clear()
1081 for (i = 0; i < count; i++) in b43_clear_keys()
1108 for (index = 0; index < count; index++) { in b43_dump_keymemory()
1113 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { in b43_dump_keymemory()
1115 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF)); in b43_dump_keymemory()
1126 for (i = 0; i < 14; i += 2) { in b43_dump_keymemory()
1128 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF)); in b43_dump_keymemory()
1132 ((index - pairwise_keys_start) * 2) + 0); in b43_dump_keymemory()
1135 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0); in b43_dump_keymemory()
1192 for (i = 0; i < 100; i++) { in b43_power_saving_ctl_bits()
1213 bcma_cc_write32(bcma_cc, BCMA_CC_PMU_CHIPCTL_ADDR, 0); in b43_wireless_core_phy_pll_reset()
1214 bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4); in b43_wireless_core_phy_pll_reset()
1215 bcma_cc_set32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, 0x4); in b43_wireless_core_phy_pll_reset()
1216 bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4); in b43_wireless_core_phy_pll_reset()
1223 chipco_write32(ssb_cc, SSB_CHIPCO_CHIPCTL_ADDR, 0); in b43_wireless_core_phy_pll_reset()
1224 chipco_mask32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, ~0x4); in b43_wireless_core_phy_pll_reset()
1225 chipco_set32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, 0x4); in b43_wireless_core_phy_pll_reset()
1226 chipco_mask32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, ~0x4); in b43_wireless_core_phy_pll_reset()
1265 tmp |= 0x100; in b43_bcma_wireless_core_reset()
1286 u32 flags = 0; in b43_ssb_wireless_core_reset()
1341 if (!(v0 & 0x00000001)) in handle_irq_transmit_status()
1346 stat.seq = (v1 & 0x0000FFFF); in handle_irq_transmit_status()
1347 stat.phy_stat = ((v1 & 0x00FF0000) >> 16); in handle_irq_transmit_status()
1348 tmp = (v0 & 0x0000FFFF); in handle_irq_transmit_status()
1349 stat.frame_count = ((tmp & 0xF000) >> 12); in handle_irq_transmit_status()
1350 stat.rts_count = ((tmp & 0x0F00) >> 8); in handle_irq_transmit_status()
1351 stat.supp_reason = ((tmp & 0x001C) >> 2); in handle_irq_transmit_status()
1352 stat.pm_indicated = !!(tmp & 0x0080); in handle_irq_transmit_status()
1353 stat.intermediate = !!(tmp & 0x0040); in handle_irq_transmit_status()
1354 stat.for_ampdu = !!(tmp & 0x0020); in handle_irq_transmit_status()
1355 stat.acked = !!(tmp & 0x0002); in handle_irq_transmit_status()
1372 if (!(dummy & 0x00000001)) in drain_txstatus_queue()
1380 u32 val = 0; in b43_jssi_read()
1392 (jssi & 0x0000FFFF)); in b43_jssi_write()
1394 (jssi & 0xFFFF0000) >> 16); in b43_jssi_write()
1399 b43_jssi_write(dev, 0x7F7F7F7F); in b43_generate_noise_sample()
1413 dev->noisecalc.nr_samples = 0; in b43_calculate_link_quality()
1442 if (noise[0] == 0x7F || noise[1] == 0x7F || in handle_irq_noise()
1443 noise[2] == 0x7F || noise[3] == 0x7F) in handle_irq_noise()
1449 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); in handle_irq_noise()
1450 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); in handle_irq_noise()
1451 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); in handle_irq_noise()
1452 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); in handle_irq_noise()
1453 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]]; in handle_irq_noise()
1460 average = 0; in handle_irq_noise()
1461 for (i = 0; i < 8; i++) { in handle_irq_noise()
1462 for (j = 0; j < 4; j++) in handle_irq_noise()
1469 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C); in handle_irq_noise()
1470 tmp = (tmp / 128) & 0x1F; in handle_irq_noise()
1494 b43_power_saving_ctl_bits(dev, 0); in handle_irq_tbtt_indication()
1518 if (!(tmp & 0x00000008)) in handle_irq_pmq()
1522 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002); in handle_irq_pmq()
1533 plcp.data = 0; in b43_write_template_common()
1540 tmp = (u32) (data[0]) << 16; in b43_write_template_common()
1545 tmp = (u32) (data[i + 0]); in b43_write_template_common()
1566 if (antenna_nr == 0) { in b43_ieee80211_antenna_sanitize()
1568 return 0; in b43_ieee80211_antenna_sanitize()
1579 return 0; in b43_ieee80211_antenna_sanitize()
1602 return 0; in b43_antenna_to_phyctl()
1635 0x200 - sizeof(struct b43_plcp_hdr6)); in b43_write_beacon_template()
1659 for (i = 0; i < variable_len - 2; ) { in b43_write_beacon_template()
1700 B43_SHM_SH_DTIMPER, 0); in b43_write_beacon_template()
1702 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset); in b43_write_beacon_template()
1835 beacon = ieee80211_beacon_get(wl->hw, wl->vif, 0); in b43_update_templates()
1859 b43_write16(dev, 0x606, (beacon_int >> 6)); in b43_set_beacon_int()
1860 b43_write16(dev, 0x610, beacon_int); in b43_set_beacon_int()
1915 for (i = 0; i < 4096; i += 2) { in handle_irq_ucode_debug()
1928 for (i = 0, cnt = 0; i < 64; i++) { in handle_irq_ucode_debug()
1930 if (cnt == 0) in handle_irq_ucode_debug()
1932 printk("r%02u: 0x%04X ", i, tmp); in handle_irq_ucode_debug()
1936 cnt = 0; in handle_irq_ucode_debug()
1966 u32 merged_dma_reason = 0; in b43_do_interrupt_thread()
1973 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) { in b43_do_interrupt_thread()
1995 "Fatal DMA error: 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X\n", in b43_do_interrupt_thread()
1996 dma_reason[0], dma_reason[1], in b43_do_interrupt_thread()
2024 if (dma_reason[0] & B43_DMAIRQ_RDESC_UFLOW) { in b43_do_interrupt_thread()
2029 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) { in b43_do_interrupt_thread()
2050 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) { in b43_do_interrupt_thread()
2078 if (reason == 0xffffffff) /* shared IRQ */ in b43_do_interrupt()
2084 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON) in b43_do_interrupt()
2085 & 0x0001FC00; in b43_do_interrupt()
2087 & 0x0000DC00; in b43_do_interrupt()
2089 & 0x0000DC00; in b43_do_interrupt()
2091 & 0x0001DC00; in b43_do_interrupt()
2093 & 0x0000DC00; in b43_do_interrupt()
2096 & 0x0000DC00; in b43_do_interrupt()
2101 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]); in b43_do_interrupt()
2111 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); in b43_do_interrupt()
2200 return 0; in b43_do_request_fw()
2204 (strcmp(fw->filename, name) == 0)) in b43_do_request_fw()
2205 return 0; /* Already have this fw. */ in b43_do_request_fw()
2235 if (err < 0) { in b43_do_request_fw()
2284 return 0; in b43_do_request_fw()
2513 return 0; in b43_try_request_fw()
2580 for (i = 0; i < B43_NR_FWTYPES; i++) { in b43_request_firmware()
2615 int err = 0; in b43_upload_microcode()
2617 /* Jump the microcode PSM to offset 0 */ in b43_upload_microcode()
2623 for (i = 0; i < 64; i++) in b43_upload_microcode()
2624 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0); in b43_upload_microcode()
2625 for (i = 0; i < 4096; i += 2) in b43_upload_microcode()
2626 b43_shm_write16(dev, B43_SHM_SHARED, i, 0); in b43_upload_microcode()
2631 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000); in b43_upload_microcode()
2632 for (i = 0; i < len; i++) { in b43_upload_microcode()
2641 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA); in b43_upload_microcode()
2642 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000); in b43_upload_microcode()
2644 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB); in b43_upload_microcode()
2645 for (i = 0; i < len; i++) { in b43_upload_microcode()
2658 i = 0; in b43_upload_microcode()
2680 if (fwrev <= 0x128) { in b43_upload_microcode()
2696 WARN_ON(dev->fw.opensource != (fwdate == 0xFFFF)); in b43_upload_microcode()
2722 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF, in b43_upload_microcode()
2723 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F); in b43_upload_microcode()
2727 b43_print_fw_helptext(dev->wl, 0); in b43_upload_microcode()
2741 b43_print_fw_helptext(dev->wl, 0); in b43_upload_microcode()
2744 return 0; in b43_upload_microcode()
2766 for (i = 0; i < count; i++) { in b43_write_initvals()
2773 if (offset >= 0x1000) in b43_write_initvals()
2806 return 0; in b43_write_initvals()
2839 return 0; in b43_upload_initvals_band()
2872 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0); in b43_gpio_init()
2873 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF); in b43_gpio_init()
2875 mask = 0x0000001F; in b43_gpio_init()
2876 set = 0x0000000F; in b43_gpio_init()
2877 if (dev->dev->chip_id == 0x4301) { in b43_gpio_init()
2878 mask |= 0x0060; in b43_gpio_init()
2879 set |= 0x0060; in b43_gpio_init()
2880 } else if (dev->dev->chip_id == 0x5354) { in b43_gpio_init()
2882 set &= 0x2; /* 0x2 is LED GPIO on BCM5354 */ in b43_gpio_init()
2885 if (0 /* FIXME: conditional unknown */ ) { in b43_gpio_init()
2888 | 0x0100); in b43_gpio_init()
2890 mask |= 0x0080; in b43_gpio_init()
2891 set |= 0x0080; in b43_gpio_init()
2893 mask |= 0x0100; in b43_gpio_init()
2894 set |= 0x0100; in b43_gpio_init()
2900 | 0x0200); in b43_gpio_init()
2901 mask |= 0x0200; in b43_gpio_init()
2902 set |= 0x0200; in b43_gpio_init()
2922 return 0; in b43_gpio_init()
2935 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, ~0, 0); in b43_gpio_cleanup()
2942 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0); in b43_gpio_cleanup()
2965 B43_WARN_ON(dev->mac_suspended < 0); in b43_mac_enable()
2966 if (dev->mac_suspended == 0) { in b43_mac_enable()
2967 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED); in b43_mac_enable()
2973 b43_power_saving_ctl_bits(dev, 0); in b43_mac_enable()
2984 B43_WARN_ON(dev->mac_suspended < 0); in b43_mac_suspend()
2986 if (dev->mac_suspended == 0) { in b43_mac_suspend()
2988 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0); in b43_mac_suspend()
3046 case 2: /* 168 Mhz: 2^26/168 = 0x61862 */ in b43_mac_switch_freq()
3047 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x1862); in b43_mac_switch_freq()
3048 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6); in b43_mac_switch_freq()
3050 case 1: /* 164 Mhz: 2^26/164 = 0x63e70 */ in b43_mac_switch_freq()
3051 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x3e70); in b43_mac_switch_freq()
3052 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6); in b43_mac_switch_freq()
3054 default: /* 160 Mhz: 2^26/160 = 0x66666 */ in b43_mac_switch_freq()
3055 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x6666); in b43_mac_switch_freq()
3056 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6); in b43_mac_switch_freq()
3068 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x2082); in b43_mac_switch_freq()
3069 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8); in b43_mac_switch_freq()
3072 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x5341); in b43_mac_switch_freq()
3073 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8); in b43_mac_switch_freq()
3076 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x8889); in b43_mac_switch_freq()
3077 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8); in b43_mac_switch_freq()
3083 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x7CE0); in b43_mac_switch_freq()
3084 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC); in b43_mac_switch_freq()
3087 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0xCCCD); in b43_mac_switch_freq()
3088 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC); in b43_mac_switch_freq()
3135 if (dev->dev->chip_id == 0x4306 && in b43_adjust_opmode()
3141 b43_write16(dev, 0x612, cfp_pretbtt); in b43_adjust_opmode()
3147 if (0 /* ctl & B43_MACCTL_AP */) in b43_adjust_opmode()
3148 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0); in b43_adjust_opmode()
3150 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ); in b43_adjust_opmode()
3158 offset = 0x480; in b43_rate_memory_write()
3159 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2; in b43_rate_memory_write()
3161 offset = 0x4C0; in b43_rate_memory_write()
3162 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2; in b43_rate_memory_write()
3164 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20, in b43_rate_memory_write()
3186 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0); in b43_rate_memory_init()
3187 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0); in b43_rate_memory_init()
3188 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0); in b43_rate_memory_init()
3189 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0); in b43_rate_memory_init()
3199 u16 ctl = 0; in b43_set_phytxctl_defaults()
3285 value16 = b43_read16(dev, 0x005E); in b43_chip_init()
3286 value16 |= 0x0004; in b43_chip_init()
3287 b43_write16(dev, 0x005E, value16); in b43_chip_init()
3289 b43_write32(dev, 0x0100, 0x01000000); in b43_chip_init()
3291 b43_write32(dev, 0x010C, 0x01000000); in b43_chip_init()
3293 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0); in b43_chip_init()
3294 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA); in b43_chip_init()
3297 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */ in b43_chip_init()
3298 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 0); in b43_chip_init()
3304 b43_write16(dev, 0x060E, 0x0000); in b43_chip_init()
3305 b43_write16(dev, 0x0610, 0x8000); in b43_chip_init()
3306 b43_write16(dev, 0x0604, 0x0000); in b43_chip_init()
3307 b43_write16(dev, 0x0606, 0x0200); in b43_chip_init()
3309 b43_write32(dev, 0x0188, 0x80000000); in b43_chip_init()
3310 b43_write32(dev, 0x018C, 0x02000000); in b43_chip_init()
3312 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000); in b43_chip_init()
3313 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001FC00); in b43_chip_init()
3314 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00); in b43_chip_init()
3315 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00); in b43_chip_init()
3316 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00); in b43_chip_init()
3317 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00); in b43_chip_init()
3318 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00); in b43_chip_init()
3325 /* FIXME: 0xE74 is quite common, but should be read from CC */ in b43_chip_init()
3326 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74); in b43_chip_init()
3337 err = 0; in b43_chip_init()
3371 * It will reset the watchdog counter to 0 in its idle loop. */ in b43_periodic_every15sec()
3397 dev->irq_count = 0; in b43_periodic_every15sec()
3398 dev->tx_count = 0; in b43_periodic_every15sec()
3399 dev->rx_count = 0; in b43_periodic_every15sec()
3400 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) { in b43_periodic_every15sec()
3402 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n", in b43_periodic_every15sec()
3404 dev->irq_bit_count[i] = 0; in b43_periodic_every15sec()
3416 if (state % 4 == 0) in do_periodic_work()
3418 if (state % 2 == 0) in do_periodic_work()
3459 dev->periodic_state = 0; in b43_periodic_tasks_setup()
3461 ieee80211_queue_delayed_work(dev->wl->hw, work, 0); in b43_periodic_tasks_setup()
3469 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0); in b43_validate_chipaccess()
3473 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55); in b43_validate_chipaccess()
3474 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55) in b43_validate_chipaccess()
3476 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA); in b43_validate_chipaccess()
3477 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA) in b43_validate_chipaccess()
3482 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122); in b43_validate_chipaccess()
3483 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344); in b43_validate_chipaccess()
3484 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566); in b43_validate_chipaccess()
3485 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788); in b43_validate_chipaccess()
3486 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344) in b43_validate_chipaccess()
3488 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD); in b43_validate_chipaccess()
3489 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 || in b43_validate_chipaccess()
3490 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD || in b43_validate_chipaccess()
3491 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB || in b43_validate_chipaccess()
3492 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788) in b43_validate_chipaccess()
3495 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0); in b43_validate_chipaccess()
3501 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA); in b43_validate_chipaccess()
3502 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB); in b43_validate_chipaccess()
3503 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB) in b43_validate_chipaccess()
3505 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC) in b43_validate_chipaccess()
3508 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0); in b43_validate_chipaccess()
3515 return 0; in b43_validate_chipaccess()
3563 int err = 0; in b43_rng_init()
3589 int err = 0; in b43_tx_work()
3598 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) { in b43_tx_work()
3613 err = 0; in b43_tx_work()
3661 memset(¶ms, 0, sizeof(params)); in b43_qos_params_upload()
3671 for (i = 0; i < ARRAY_SIZE(params); i++) { in b43_qos_params_upload()
3676 tmp |= 0x100; in b43_qos_params_upload()
3691 [0] = B43_QOS_VOICE,
3711 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) { in b43_qos_upload_all()
3729 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) { in b43_qos_clear()
3734 params->p.txop = 0; in b43_qos_clear()
3736 params->p.cw_min = 0x0001; in b43_qos_clear()
3737 params->p.cw_max = 0x0001; in b43_qos_clear()
3740 params->p.txop = 0; in b43_qos_clear()
3742 params->p.cw_min = 0x0001; in b43_qos_clear()
3743 params->p.cw_max = 0x0001; in b43_qos_clear()
3746 params->p.txop = 0; in b43_qos_clear()
3748 params->p.cw_min = 0x0001; in b43_qos_clear()
3749 params->p.cw_max = 0x03FF; in b43_qos_clear()
3752 params->p.txop = 0; in b43_qos_clear()
3754 params->p.cw_min = 0x0001; in b43_qos_clear()
3755 params->p.cw_max = 0x03FF; in b43_qos_clear()
3801 return 0; in b43_op_conf_tx()
3816 err = 0; in b43_op_conf_tx()
3833 return 0; in b43_op_get_stats()
3848 tsf = 0; in b43_op_get_tsf()
3913 return 0; in b43_switch_band()
3953 return 0; in b43_switch_band()
3958 interval = min_t(u16, interval, (u16)0xFF); in b43_set_beacon_listen_interval()
3969 short_retry = min(short_retry, (unsigned int)0xF); in b43_set_retry_limits()
3970 long_retry = min(long_retry, (unsigned int)0xF); in b43_set_retry_limits()
3985 int err = 0; in b43_op_config()
4018 if (conf->power_level != 0) { in b43_op_config()
4063 for (i = 0; i < sband->n_bitrates; i++) { in b43_update_basic_rates()
4070 offset &= 0xF; in b43_update_basic_rates()
4075 offset &= 0xF; in b43_update_basic_rates()
4082 basic_offset &= 0xF; in b43_update_basic_rates()
4085 basic_offset &= 0xF; in b43_update_basic_rates()
4168 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; in b43_op_set_key()
4294 *fflags = 0; in b43_op_configure_filter()
4354 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); in b43_wireless_core_stop()
4358 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); in b43_wireless_core_stop()
4379 B43_WARN_ON(mask != 0xFFFFFFFF && mask); in b43_wireless_core_stop()
4382 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) { in b43_wireless_core_stop()
4483 int unsupported = 0; in b43_phy_versioning()
4548 radio_manuf = 0x17F; in b43_phy_versioning()
4550 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, 0); in b43_phy_versioning()
4556 radio_ver = 0; /* Is there version somewhere? */ in b43_phy_versioning()
4560 for (tmp = 0; tmp < 3; tmp++) { in b43_phy_versioning()
4565 radio_manuf = 0x17F; in b43_phy_versioning()
4567 radio_rev = (radio24[0] & 0xF); in b43_phy_versioning()
4568 radio_ver = (radio24[0] & 0xF0) >> 4; in b43_phy_versioning()
4570 if (dev->dev->chip_id == 0x4317) { in b43_phy_versioning()
4571 if (dev->dev->chip_rev == 0) in b43_phy_versioning()
4572 tmp = 0x3205017F; in b43_phy_versioning()
4574 tmp = 0x4205017F; in b43_phy_versioning()
4576 tmp = 0x5205017F; in b43_phy_versioning()
4585 radio_manuf = (tmp & 0x00000FFF); in b43_phy_versioning()
4586 radio_id = (tmp & 0x0FFFF000) >> 12; in b43_phy_versioning()
4587 radio_rev = (tmp & 0xF0000000) >> 28; in b43_phy_versioning()
4588 radio_ver = 0; /* Probably not available on old hw */ in b43_phy_versioning()
4591 if (radio_manuf != 0x17F /* Broadcom */) in b43_phy_versioning()
4595 if ((radio_id & 0xFFF0) != 0x2050) in b43_phy_versioning()
4599 if (radio_id != 0x2050) in b43_phy_versioning()
4603 if (radio_id != 0x2055 && radio_id != 0x2056 && in b43_phy_versioning()
4604 radio_id != 0x2057) in b43_phy_versioning()
4606 if (radio_id == 0x2057 && in b43_phy_versioning()
4611 if (radio_id != 0x2062 && radio_id != 0x2063) in b43_phy_versioning()
4615 if (radio_id != 0x2059) in b43_phy_versioning()
4619 if (radio_id != 0x2064) in b43_phy_versioning()
4623 if (radio_id != 0x2069) in b43_phy_versioning()
4631 "FOUND UNSUPPORTED RADIO (Manuf 0x%X, ID 0x%X, Revision %u, Version %u)\n", in b43_phy_versioning()
4636 "Found Radio: Manuf 0x%X, ID 0x%X, Revision %u, Version %u\n", in b43_phy_versioning()
4648 return 0; in b43_phy_versioning()
4674 memset(&dev->stats, 0, sizeof(dev->stats)); in setup_struct_wldev_for_init()
4679 dev->irq_reason = 0; in setup_struct_wldev_for_init()
4680 memset(dev->dma_reason, 0, sizeof(dev->dma_reason)); in setup_struct_wldev_for_init()
4688 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc)); in setup_struct_wldev_for_init()
4732 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) || in b43_imcfglo_timeouts_workaround()
4733 (bus->chip_id == 0x4312)) { in b43_imcfglo_timeouts_workaround()
4737 tmp |= 0x3; in b43_imcfglo_timeouts_workaround()
4751 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8)) in b43_set_synth_pu_delay()
4801 dev->phy.ops->switch_analog(dev, 0); in b43_wireless_core_exit()
4807 b43_device_disable(dev, 0); in b43_wireless_core_exit()
4821 err = b43_bus_powerup(dev, 0); in b43_wireless_core_init()
4868 if (phy->radio_ver == 0x2050) { in b43_wireless_core_init()
4890 mac_hw_cap & 0xffff); in b43_wireless_core_init()
4892 (mac_hw_cap >> 16) & 0xffff); in b43_wireless_core_init()
4911 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F); in b43_wireless_core_init()
4913 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF); in b43_wireless_core_init()
4915 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF); in b43_wireless_core_init()
4989 b43_set_synth_pu_delay(dev, 0); in b43_op_add_interface()
4992 err = 0; in b43_op_add_interface()
4996 if (err == 0) in b43_op_add_interface()
4997 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0); in b43_op_add_interface()
5029 int did_init = 0; in b43_op_start()
5030 int err = 0; in b43_op_start()
5037 wl->filter_flags = 0; in b43_op_start()
5076 b43_op_config(hw, ~0); in b43_op_start()
5113 return 0; in b43_op_beacon_set_tim()
5164 if (idx != 0) in b43_op_get_survey()
5171 return 0; in b43_op_get_survey()
5210 int err = 0; in b43_chip_reset()
5251 b43_op_config(wl->hw, ~0); in b43_chip_reset()
5253 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0); in b43_chip_reset()
5267 limited_2g = phy->radio_ver == 0x2057 && in b43_setup_bands()
5269 limited_5g = phy->radio_ver == 0x2057 && in b43_setup_bands()
5288 return 0; in b43_setup_bands()
5302 u16 dev_id = 0; in b43_supported_bands()
5320 case 0x4324: /* BCM4306 */ in b43_supported_bands()
5321 case 0x4312: /* BCM4311 */ in b43_supported_bands()
5322 case 0x4319: /* BCM4318 */ in b43_supported_bands()
5323 case 0x4328: /* BCM4321 */ in b43_supported_bands()
5324 case 0x432b: /* BCM4322 */ in b43_supported_bands()
5325 case 0x4350: /* BCM43222 */ in b43_supported_bands()
5326 case 0x4353: /* BCM43224 */ in b43_supported_bands()
5327 case 0x0576: /* BCM43224 */ in b43_supported_bands()
5328 case 0x435f: /* BCM6362 */ in b43_supported_bands()
5329 case 0x4331: /* BCM4331 */ in b43_supported_bands()
5330 case 0x4359: /* BCM43228 */ in b43_supported_bands()
5331 case 0x43a0: /* BCM4360 */ in b43_supported_bands()
5332 case 0x43b1: /* BCM4352 */ in b43_supported_bands()
5337 case 0x4321: /* BCM4306 */ in b43_supported_bands()
5342 case 0x4313: /* BCM4311 */ in b43_supported_bands()
5343 case 0x431a: /* BCM4318 */ in b43_supported_bands()
5344 case 0x432a: /* BCM4321 */ in b43_supported_bands()
5345 case 0x432d: /* BCM4322 */ in b43_supported_bands()
5346 case 0x4352: /* BCM43222 */ in b43_supported_bands()
5347 case 0x435a: /* BCM43228 */ in b43_supported_bands()
5348 case 0x4333: /* BCM4331 */ in b43_supported_bands()
5349 case 0x43a2: /* BCM4360 */ in b43_supported_bands()
5350 case 0x43b3: /* BCM4352 */ in b43_supported_bands()
5387 err = b43_bus_powerup(dev, 0); in b43_wireless_core_attach()
5463 dev->phy.ops->switch_analog(dev, 0); in b43_wireless_core_attach()
5464 b43_device_disable(dev, 0); in b43_wireless_core_attach()
5536 bus->chip_id == 0x4301 && bus->sprom.board_rev == 0x74) in b43_sprom_fixup()
5539 bus->boardinfo.type == 0x4E && bus->sprom.board_rev > 0x40) in b43_sprom_fixup()
5543 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) || in b43_sprom_fixup()
5544 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) || in b43_sprom_fixup()
5545 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) || in b43_sprom_fixup()
5546 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) || in b43_sprom_fixup()
5547 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) || in b43_sprom_fixup()
5548 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) || in b43_sprom_fixup()
5549 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010)) in b43_sprom_fixup()
5610 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) { in b43_wireless_init()
5616 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id); in b43_wireless_init()
5630 (core->id.rev == 0x17 || core->id.rev == 0x18)) { in b43_bcma_probe()
5631 …pr_err("Support for cores revisions 0x17 and 0x18 disabled by module param allhwsupport=0. Try b43… in b43_bcma_probe()