Lines Matching +full:channel +full:- +full:spacing
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
27 #include "hw-ops.h"
42 struct ath9k_channel *chan = ah->curchan; in ath9k_hw_set_clockrate()
52 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) in ath9k_hw_set_clockrate()
66 common->clockrate = clockrate; in ath9k_hw_set_clockrate()
73 return usecs * common->clockrate; in ath9k_hw_mac_to_clks()
116 for (r = 0; r < array->ia_rows; r++) { in ath9k_hw_write_array()
131 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__); in ath9k_hw_read_array()
137 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__); in ath9k_hw_read_array()
185 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { in ath9k_hw_computetxtime()
193 } else if (ah->curchan && in ath9k_hw_computetxtime()
194 IS_CHAN_HALF_RATE(ah->curchan)) { in ath9k_hw_computetxtime()
228 centers->ctl_center = centers->ext_center = in ath9k_hw_get_channel_centers()
229 centers->synth_center = chan->channel; in ath9k_hw_get_channel_centers()
234 centers->synth_center = in ath9k_hw_get_channel_centers()
235 chan->channel + HT40_CHANNEL_CENTER_SHIFT; in ath9k_hw_get_channel_centers()
238 centers->synth_center = in ath9k_hw_get_channel_centers()
239 chan->channel - HT40_CHANNEL_CENTER_SHIFT; in ath9k_hw_get_channel_centers()
240 extoff = -1; in ath9k_hw_get_channel_centers()
243 centers->ctl_center = in ath9k_hw_get_channel_centers()
244 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); in ath9k_hw_get_channel_centers()
245 /* 25 MHz spacing is supported by hw but not on upper layers */ in ath9k_hw_get_channel_centers()
246 centers->ext_center = in ath9k_hw_get_channel_centers()
247 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); in ath9k_hw_get_channel_centers()
259 if (ah->get_mac_revision) in ath9k_hw_read_revisions()
260 ah->hw_version.macRev = ah->get_mac_revision(); in ath9k_hw_read_revisions()
262 switch (ah->hw_version.devid) { in ath9k_hw_read_revisions()
264 ah->hw_version.macVersion = AR_SREV_VERSION_9100; in ath9k_hw_read_revisions()
267 ah->hw_version.macVersion = AR_SREV_VERSION_9330; in ath9k_hw_read_revisions()
268 if (!ah->get_mac_revision) { in ath9k_hw_read_revisions()
270 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); in ath9k_hw_read_revisions()
274 ah->hw_version.macVersion = AR_SREV_VERSION_9340; in ath9k_hw_read_revisions()
277 ah->hw_version.macVersion = AR_SREV_VERSION_9550; in ath9k_hw_read_revisions()
280 ah->hw_version.macVersion = AR_SREV_VERSION_9531; in ath9k_hw_read_revisions()
283 ah->hw_version.macVersion = AR_SREV_VERSION_9561; in ath9k_hw_read_revisions()
289 if (srev == -1) { in ath9k_hw_read_revisions()
299 ah->hw_version.macVersion = in ath9k_hw_read_revisions()
301 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); in ath9k_hw_read_revisions()
304 ah->is_pciexpress = true; in ath9k_hw_read_revisions()
306 ah->is_pciexpress = (val & in ath9k_hw_read_revisions()
310 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); in ath9k_hw_read_revisions()
312 ah->hw_version.macRev = val & AR_SREV_REVISION; in ath9k_hw_read_revisions()
314 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) in ath9k_hw_read_revisions()
315 ah->is_pciexpress = true; in ath9k_hw_read_revisions()
371 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", in ath9k_hw_chip_test()
382 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", in ath9k_hw_chip_test()
398 ah->config.dma_beacon_response_time = 1; in ath9k_hw_init_config()
399 ah->config.sw_beacon_response_time = 6; in ath9k_hw_init_config()
400 ah->config.cwm_ignore_extcca = false; in ath9k_hw_init_config()
401 ah->config.analog_shiftreg = 1; in ath9k_hw_init_config()
403 ah->config.rx_intr_mitigation = true; in ath9k_hw_init_config()
406 ah->config.rimt_last = 500; in ath9k_hw_init_config()
407 ah->config.rimt_first = 2000; in ath9k_hw_init_config()
409 ah->config.rimt_last = 250; in ath9k_hw_init_config()
410 ah->config.rimt_first = 700; in ath9k_hw_init_config()
414 ah->config.pll_pwrsave = 7; in ath9k_hw_init_config()
418 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). in ath9k_hw_init_config()
429 * This issue is not present on PCI-Express devices or pre-AR5416 in ath9k_hw_init_config()
433 ah->config.serialize_regmode = SER_REG_MODE_AUTO; in ath9k_hw_init_config()
435 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { in ath9k_hw_init_config()
436 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || in ath9k_hw_init_config()
438 !ah->is_pciexpress)) { in ath9k_hw_init_config()
439 ah->config.serialize_regmode = SER_REG_MODE_ON; in ath9k_hw_init_config()
441 ah->config.serialize_regmode = SER_REG_MODE_OFF; in ath9k_hw_init_config()
446 ah->config.serialize_regmode); in ath9k_hw_init_config()
449 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; in ath9k_hw_init_config()
451 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; in ath9k_hw_init_config()
458 regulatory->country_code = CTRY_DEFAULT; in ath9k_hw_init_defaults()
459 regulatory->power_limit = MAX_COMBINED_POWER; in ath9k_hw_init_defaults()
461 ah->hw_version.magic = AR5416_MAGIC; in ath9k_hw_init_defaults()
462 ah->hw_version.subvendorid = 0; in ath9k_hw_init_defaults()
464 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE | in ath9k_hw_init_defaults()
467 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; in ath9k_hw_init_defaults()
469 ah->slottime = 9; in ath9k_hw_init_defaults()
470 ah->globaltxtimeout = (u32) -1; in ath9k_hw_init_defaults()
471 ah->power_mode = ATH9K_PM_UNDEFINED; in ath9k_hw_init_defaults()
472 ah->htc_reset_init = true; in ath9k_hw_init_defaults()
474 ah->tpc_enabled = false; in ath9k_hw_init_defaults()
476 ah->ani_function = ATH9K_ANI_ALL; in ath9k_hw_init_defaults()
478 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; in ath9k_hw_init_defaults()
481 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); in ath9k_hw_init_defaults()
483 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); in ath9k_hw_init_defaults()
494 if (is_valid_ether_addr(common->macaddr)) in ath9k_hw_init_macaddr()
498 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); in ath9k_hw_init_macaddr()
499 common->macaddr[2 * i] = eeval >> 8; in ath9k_hw_init_macaddr()
500 common->macaddr[2 * i + 1] = eeval & 0xff; in ath9k_hw_init_macaddr()
503 if (is_valid_ether_addr(common->macaddr)) in ath9k_hw_init_macaddr()
507 common->macaddr); in ath9k_hw_init_macaddr()
509 eth_random_addr(common->macaddr); in ath9k_hw_init_macaddr()
511 common->macaddr); in ath9k_hw_init_macaddr()
521 if (common->bus_ops->ath_bus_type != ATH_USB) { in ath9k_hw_post_init()
523 return -ENODEV; in ath9k_hw_post_init()
537 ah->eep_ops->get_eeprom_ver(ah), in ath9k_hw_post_init()
538 ah->eep_ops->get_eeprom_rev(ah)); in ath9k_hw_post_init()
547 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0); in ath9k_hw_post_init()
549 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ; in ath9k_hw_post_init()
550 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ; in ath9k_hw_post_init()
574 return -EOPNOTSUPP; in __ath9k_hw_init()
577 switch (ah->hw_version.macVersion) { in __ath9k_hw_init()
599 ah->hw_version.macVersion, ah->hw_version.macRev); in __ath9k_hw_init()
600 return -EOPNOTSUPP; in __ath9k_hw_init()
609 ah->WARegVal = REG_READ(ah, AR_WA(ah)); in __ath9k_hw_init()
610 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | in __ath9k_hw_init()
616 return -EIO; in __ath9k_hw_init()
620 ah->WARegVal |= AR_WA_BIT22; in __ath9k_hw_init()
621 REG_WRITE(ah, AR_WA(ah), ah->WARegVal); in __ath9k_hw_init()
633 return -EIO; in __ath9k_hw_init()
638 ah->is_pciexpress = false; in __ath9k_hw_init()
640 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); in __ath9k_hw_init()
643 if (!ah->is_pciexpress) in __ath9k_hw_init()
658 common->state = ATH_HW_INITIALIZED; in __ath9k_hw_init()
669 switch (ah->hw_version.devid) { in ath9k_hw_init()
693 if (common->bus_ops->ath_bus_type == ATH_USB) in ath9k_hw_init()
696 ah->hw_version.devid); in ath9k_hw_init()
697 return -EOPNOTSUPP; in ath9k_hw_init()
800 if (ah->is_clk_25mhz) { in ath9k_hw_init_pll()
842 if (ah->is_clk_25mhz) { in ath9k_hw_init_pll()
948 if (ah->config.rx_intr_mitigation) { in ath9k_hw_init_interrupt_masks()
956 if (ah->config.rx_intr_mitigation) { in ath9k_hw_init_interrupt_masks()
965 if (ah->config.tx_intr_mitigation) { in ath9k_hw_init_interrupt_masks()
976 ah->imrs2_reg |= AR_IMR_S2_GTT; in ath9k_hw_init_interrupt_masks()
977 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); in ath9k_hw_init_interrupt_masks()
979 if (ah->msi_enabled) { in ath9k_hw_init_interrupt_masks()
980 ah->msi_reg = REG_READ(ah, AR_PCIE_MSI(ah)); in ath9k_hw_init_interrupt_masks()
981 ah->msi_reg |= AR_PCIE_MSI_HW_DBI_WR_EN; in ath9k_hw_init_interrupt_masks()
982 ah->msi_reg &= AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64; in ath9k_hw_init_interrupt_masks()
1007 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); in ath9k_hw_set_sifs_time()
1038 ah->globaltxtimeout = (u32) -1; in ath9k_hw_set_global_txtimeout()
1042 ah->globaltxtimeout = tu; in ath9k_hw_set_global_txtimeout()
1050 const struct ath9k_channel *chan = ah->curchan; in ath9k_hw_init_global_settings()
1057 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", in ath9k_hw_init_global_settings()
1058 ah->misc_mode); in ath9k_hw_init_global_settings()
1063 if (ah->misc_mode != 0) in ath9k_hw_init_global_settings()
1064 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); in ath9k_hw_init_global_settings()
1090 rx_lat = (rx_lat * 4) - 1; in ath9k_hw_init_global_settings()
1105 common->clockrate; in ath9k_hw_init_global_settings()
1111 slottime = ah->slottime; in ath9k_hw_init_global_settings()
1114 /* As defined by IEEE 802.11-2007 17.3.8.6 */ in ath9k_hw_init_global_settings()
1115 slottime += 3 * ah->coverage_class; in ath9k_hw_init_global_settings()
1128 acktimeout += 64 - sifstime - ah->slottime; in ath9k_hw_init_global_settings()
1129 ctstimeout += 48 - sifstime - ah->slottime; in ath9k_hw_init_global_settings()
1132 if (ah->dynack.enabled) { in ath9k_hw_init_global_settings()
1133 acktimeout = ah->dynack.ackto; in ath9k_hw_init_global_settings()
1135 slottime = (acktimeout - 3) / 2; in ath9k_hw_init_global_settings()
1137 ah->dynack.ackto = acktimeout; in ath9k_hw_init_global_settings()
1144 if (ah->globaltxtimeout != (u32) -1) in ath9k_hw_init_global_settings()
1145 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); in ath9k_hw_init_global_settings()
1149 (common->clockrate - 1) | in ath9k_hw_init_global_settings()
1165 if (common->state < ATH_HW_INITIALIZED) in ath9k_hw_deinit()
1178 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); in ath9k_regd_get_ctl()
1189 /* Reset and Channel Switching Routines */
1213 * Restore TX Trigger Level to its pre-reset value. in ath9k_hw_set_dma()
1218 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); in ath9k_hw_set_dma()
1236 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - in ath9k_hw_set_dma()
1237 ah->caps.rx_status_len); in ath9k_hw_set_dma()
1289 if (!ah->is_monitoring) in ath9k_hw_set_operating_mode()
1302 for (coef_exp = 31; coef_exp > 0; coef_exp--) in ath9k_hw_get_delta_slope_vals()
1306 coef_exp = 14 - (coef_exp - COEF_SCALE_S); in ath9k_hw_get_delta_slope_vals()
1308 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); in ath9k_hw_get_delta_slope_vals()
1310 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); in ath9k_hw_get_delta_slope_vals()
1311 *coef_exponent = coef_exp - 16; in ath9k_hw_get_delta_slope_vals()
1316 * - doing a cold reset
1317 * - we have pending frames in the TX queues.
1329 if (ah->external_reset && in ath9k_hw_ar9330_reset_war()
1336 reset_err = ah->external_reset(); in ath9k_hw_ar9330_reset_war()
1364 REG_WRITE(ah, AR_WA(ah), ah->WARegVal); in ath9k_hw_set_reset()
1448 REG_WRITE(ah, AR_WA(ah), ah->WARegVal); in ath9k_hw_set_reset_power_on()
1486 REG_WRITE(ah, AR_WA(ah), ah->WARegVal); in ath9k_hw_set_reset_reg()
1493 if (!ah->reset_power_on) in ath9k_hw_set_reset_reg()
1500 ah->reset_power_on = true; in ath9k_hw_set_reset_reg()
1519 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) in ath9k_hw_chip_reset()
1523 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || in ath9k_hw_chip_reset()
1533 ah->chip_fullsleep = false; in ath9k_hw_chip_reset()
1546 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_channel_change()
1552 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) { in ath9k_hw_channel_change()
1553 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags; in ath9k_hw_channel_change()
1579 ath_err(common, "Failed to do fast channel change\n"); in ath9k_hw_channel_change()
1588 ath_err(common, "Failed to set channel\n"); in ath9k_hw_channel_change()
1598 ah->eep_ops->set_board_values(ah, chan); in ath9k_hw_channel_change()
1604 ah->ah_flags |= AH_FASTCC; in ath9k_hw_channel_change()
1606 ah->ah_flags &= ~AH_FASTCC; in ath9k_hw_channel_change()
1614 u32 gpio_mask = ah->gpio_mask; in ath9k_hw_apply_gpio_override()
1623 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); in ath9k_hw_apply_gpio_override()
1674 } while (count-- > 0); in ath9k_hw_check_alive()
1689 ah->sw_mgmt_crypto_tx = true; in ath9k_hw_init_mfp()
1691 ah->sw_mgmt_crypto_tx = false; in ath9k_hw_init_mfp()
1692 ah->sw_mgmt_crypto_rx = false; in ath9k_hw_init_mfp()
1699 ah->sw_mgmt_crypto_tx = true; in ath9k_hw_init_mfp()
1700 ah->sw_mgmt_crypto_rx = true; in ath9k_hw_init_mfp()
1702 ah->sw_mgmt_crypto_tx = true; in ath9k_hw_init_mfp()
1703 ah->sw_mgmt_crypto_rx = true; in ath9k_hw_init_mfp()
1716 | ah->sta_id1_defaults, in ath9k_hw_reset_opmode()
1726 ath9k_hw_set_operating_mode(ah, ah->opmode); in ath9k_hw_reset_opmode()
1740 ah->intr_txqs = 0; in ath9k_hw_init_queues()
1765 if (common->bus_ops->ath_bus_type == ATH_USB) { in ath9k_hw_init_desc()
1784 * Fast channel change:
1785 * (Change synthesizer based on channel freq without resetting chip)
1790 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_do_fastcc()
1793 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) in ath9k_hw_do_fastcc()
1796 if (ah->chip_fullsleep) in ath9k_hw_do_fastcc()
1799 if (!ah->curchan) in ath9k_hw_do_fastcc()
1802 if (chan->channel == ah->curchan->channel) in ath9k_hw_do_fastcc()
1805 if ((ah->curchan->channelFlags | chan->channelFlags) & in ath9k_hw_do_fastcc()
1810 * If cross-band fcc is not supoprted, bail out if channelFlags differ. in ath9k_hw_do_fastcc()
1812 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) && in ath9k_hw_do_fastcc()
1813 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT)) in ath9k_hw_do_fastcc()
1821 * re-using are present. in ath9k_hw_do_fastcc()
1823 if (AR_SREV_9462(ah) && (ah->caldata && in ath9k_hw_do_fastcc()
1824 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) || in ath9k_hw_do_fastcc()
1825 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) || in ath9k_hw_do_fastcc()
1826 !test_bit(RTT_DONE, &ah->caldata->cal_flags)))) in ath9k_hw_do_fastcc()
1829 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", in ath9k_hw_do_fastcc()
1830 ah->curchan->channel, chan->channel); in ath9k_hw_do_fastcc()
1839 ath9k_hw_loadnf(ah, ah->curchan); in ath9k_hw_do_fastcc()
1847 return -EINVAL; in ath9k_hw_do_fastcc()
1870 bool save_fullsleep = ah->chip_fullsleep; in ath9k_hw_reset()
1879 return -EIO; in ath9k_hw_reset()
1881 if (ah->curchan && !ah->chip_fullsleep) in ath9k_hw_reset()
1882 ath9k_hw_getnf(ah, ah->curchan); in ath9k_hw_reset()
1884 ah->caldata = caldata; in ath9k_hw_reset()
1885 if (caldata && (chan->channel != caldata->channel || in ath9k_hw_reset()
1886 chan->channelFlags != caldata->channelFlags)) { in ath9k_hw_reset()
1887 /* Operating channel changed, reset channel calibration data */ in ath9k_hw_reset()
1891 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags); in ath9k_hw_reset()
1893 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor); in ath9k_hw_reset()
1920 ah->paprd_table_write_done = false; in ath9k_hw_reset()
1923 if (AR_SREV_9271(ah) && ah->htc_reset_init) { in ath9k_hw_reset()
1932 return -EINVAL; in ath9k_hw_reset()
1936 if (AR_SREV_9271(ah) && ah->htc_reset_init) { in ath9k_hw_reset()
1937 ah->htc_reset_init = false; in ath9k_hw_reset()
1977 ah->eep_ops->set_board_values(ah, chan); in ath9k_hw_reset()
1988 ath9k_hw_init_interrupt_masks(ah, ah->opmode); in ath9k_hw_reset()
1992 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) in ath9k_hw_reset()
1993 ath9k_hw_gpio_request_in(ah, ah->rfkill_gpio, "ath9k-rfkill"); in ath9k_hw_reset()
2014 if (ah->config.rx_intr_mitigation) { in ath9k_hw_reset()
2015 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last); in ath9k_hw_reset()
2016 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first); in ath9k_hw_reset()
2019 if (ah->config.tx_intr_mitigation) { in ath9k_hw_reset()
2028 clear_bit(TXIQCAL_DONE, &caldata->cal_flags); in ath9k_hw_reset()
2029 clear_bit(TXCLCAL_DONE, &caldata->cal_flags); in ath9k_hw_reset()
2032 return -EIO; in ath9k_hw_reset()
2035 return -EIO; in ath9k_hw_reset()
2062 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR) in ath9k_hw_reset()
2067 if (AR_SREV_9565(ah) && common->bt_ant_diversity) in ath9k_hw_reset()
2070 if (ah->hw->conf.radar_enabled) { in ath9k_hw_reset()
2072 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan); in ath9k_hw_reset()
2085 * Notify Power Mgt is disabled in self-generated frames.
2121 REG_WRITE(ah, AR_WA(ah), ah->WARegVal & ~AR_WA_D3_L1_DISABLE); in ath9k_set_power_sleep()
2125 * Notify Power Management is enabled in self-generating
2131 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_set_power_network_sleep()
2135 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { in ath9k_set_power_network_sleep()
2145 * re-enter network sleep mode frequently, which in in ath9k_set_power_network_sleep()
2165 REG_WRITE(ah, AR_WA(ah), ah->WARegVal & ~AR_WA_D3_L1_DISABLE); in ath9k_set_power_network_sleep()
2175 REG_WRITE(ah, AR_WA(ah), ah->WARegVal); in ath9k_hw_set_power_awake()
2198 for (i = POWER_UP_TIME / 50; i > 0; i--) { in ath9k_hw_set_power_awake()
2227 "FULL-SLEEP", in ath9k_hw_setpower()
2232 if (ah->power_mode == mode) in ath9k_hw_setpower()
2235 ath_dbg(common, RESET, "%s -> %s\n", in ath9k_hw_setpower()
2236 modes[ah->power_mode], modes[mode]); in ath9k_hw_setpower()
2247 ah->chip_fullsleep = true; in ath9k_hw_setpower()
2256 ah->power_mode = mode; in ath9k_hw_setpower()
2264 if (!(ah->ah_flags & AH_UNPLUGGED)) in ath9k_hw_setpower()
2281 switch (ah->opmode) { in ath9k_hw_beaconinit()
2289 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - in ath9k_hw_beaconinit()
2290 TU_TO_USEC(ah->config.dma_beacon_response_time)); in ath9k_hw_beaconinit()
2291 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - in ath9k_hw_beaconinit()
2292 TU_TO_USEC(ah->config.sw_beacon_response_time)); in ath9k_hw_beaconinit()
2298 "%s: unsupported opmode: %d\n", __func__, ah->opmode); in ath9k_hw_beaconinit()
2316 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_set_sta_beacon_timers()
2321 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); in ath9k_hw_set_sta_beacon_timers()
2322 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); in ath9k_hw_set_sta_beacon_timers()
2323 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); in ath9k_hw_set_sta_beacon_timers()
2328 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); in ath9k_hw_set_sta_beacon_timers()
2330 beaconintval = bs->bs_intval; in ath9k_hw_set_sta_beacon_timers()
2332 if (bs->bs_sleepduration > beaconintval) in ath9k_hw_set_sta_beacon_timers()
2333 beaconintval = bs->bs_sleepduration; in ath9k_hw_set_sta_beacon_timers()
2335 dtimperiod = bs->bs_dtimperiod; in ath9k_hw_set_sta_beacon_timers()
2336 if (bs->bs_sleepduration > dtimperiod) in ath9k_hw_set_sta_beacon_timers()
2337 dtimperiod = bs->bs_sleepduration; in ath9k_hw_set_sta_beacon_timers()
2340 nextTbtt = bs->bs_nextdtim; in ath9k_hw_set_sta_beacon_timers()
2342 nextTbtt = bs->bs_nexttbtt; in ath9k_hw_set_sta_beacon_timers()
2344 ath_dbg(common, BEACON, "next DTIM %u\n", bs->bs_nextdtim); in ath9k_hw_set_sta_beacon_timers()
2351 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); in ath9k_hw_set_sta_beacon_timers()
2352 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); in ath9k_hw_set_sta_beacon_timers()
2358 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) in ath9k_hw_set_sta_beacon_timers()
2376 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); in ath9k_hw_set_sta_beacon_timers()
2394 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2409 switch (ah->hw_version.macVersion) { in ath9k_hw_dfs_tested()
2422 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_gpio_cap_init()
2425 pCap->num_gpio_pins = AR9271_NUM_GPIO; in ath9k_gpio_cap_init()
2426 pCap->gpio_mask = AR9271_GPIO_MASK; in ath9k_gpio_cap_init()
2428 pCap->num_gpio_pins = AR7010_NUM_GPIO; in ath9k_gpio_cap_init()
2429 pCap->gpio_mask = AR7010_GPIO_MASK; in ath9k_gpio_cap_init()
2431 pCap->num_gpio_pins = AR9287_NUM_GPIO; in ath9k_gpio_cap_init()
2432 pCap->gpio_mask = AR9287_GPIO_MASK; in ath9k_gpio_cap_init()
2434 pCap->num_gpio_pins = AR9285_NUM_GPIO; in ath9k_gpio_cap_init()
2435 pCap->gpio_mask = AR9285_GPIO_MASK; in ath9k_gpio_cap_init()
2437 pCap->num_gpio_pins = AR9280_NUM_GPIO; in ath9k_gpio_cap_init()
2438 pCap->gpio_mask = AR9280_GPIO_MASK; in ath9k_gpio_cap_init()
2440 pCap->num_gpio_pins = AR9300_NUM_GPIO; in ath9k_gpio_cap_init()
2441 pCap->gpio_mask = AR9300_GPIO_MASK; in ath9k_gpio_cap_init()
2443 pCap->num_gpio_pins = AR9330_NUM_GPIO; in ath9k_gpio_cap_init()
2444 pCap->gpio_mask = AR9330_GPIO_MASK; in ath9k_gpio_cap_init()
2446 pCap->num_gpio_pins = AR9340_NUM_GPIO; in ath9k_gpio_cap_init()
2447 pCap->gpio_mask = AR9340_GPIO_MASK; in ath9k_gpio_cap_init()
2449 pCap->num_gpio_pins = AR9462_NUM_GPIO; in ath9k_gpio_cap_init()
2450 pCap->gpio_mask = AR9462_GPIO_MASK; in ath9k_gpio_cap_init()
2452 pCap->num_gpio_pins = AR9485_NUM_GPIO; in ath9k_gpio_cap_init()
2453 pCap->gpio_mask = AR9485_GPIO_MASK; in ath9k_gpio_cap_init()
2455 pCap->num_gpio_pins = AR9531_NUM_GPIO; in ath9k_gpio_cap_init()
2456 pCap->gpio_mask = AR9531_GPIO_MASK; in ath9k_gpio_cap_init()
2458 pCap->num_gpio_pins = AR9550_NUM_GPIO; in ath9k_gpio_cap_init()
2459 pCap->gpio_mask = AR9550_GPIO_MASK; in ath9k_gpio_cap_init()
2461 pCap->num_gpio_pins = AR9561_NUM_GPIO; in ath9k_gpio_cap_init()
2462 pCap->gpio_mask = AR9561_GPIO_MASK; in ath9k_gpio_cap_init()
2464 pCap->num_gpio_pins = AR9565_NUM_GPIO; in ath9k_gpio_cap_init()
2465 pCap->gpio_mask = AR9565_GPIO_MASK; in ath9k_gpio_cap_init()
2467 pCap->num_gpio_pins = AR9580_NUM_GPIO; in ath9k_gpio_cap_init()
2468 pCap->gpio_mask = AR9580_GPIO_MASK; in ath9k_gpio_cap_init()
2470 pCap->num_gpio_pins = AR_NUM_GPIO; in ath9k_gpio_cap_init()
2471 pCap->gpio_mask = AR_GPIO_MASK; in ath9k_gpio_cap_init()
2477 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_fill_cap_info()
2484 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); in ath9k_hw_fill_cap_info()
2485 regulatory->current_rd = eeval; in ath9k_hw_fill_cap_info()
2487 if (ah->opmode != NL80211_IFTYPE_AP && in ath9k_hw_fill_cap_info()
2488 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { in ath9k_hw_fill_cap_info()
2489 if (regulatory->current_rd == 0x64 || in ath9k_hw_fill_cap_info()
2490 regulatory->current_rd == 0x65) in ath9k_hw_fill_cap_info()
2491 regulatory->current_rd += 5; in ath9k_hw_fill_cap_info()
2492 else if (regulatory->current_rd == 0x41) in ath9k_hw_fill_cap_info()
2493 regulatory->current_rd = 0x43; in ath9k_hw_fill_cap_info()
2495 regulatory->current_rd); in ath9k_hw_fill_cap_info()
2498 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); in ath9k_hw_fill_cap_info()
2501 if (ah->disable_5ghz) in ath9k_hw_fill_cap_info()
2504 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; in ath9k_hw_fill_cap_info()
2508 if (ah->disable_2ghz) in ath9k_hw_fill_cap_info()
2511 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; in ath9k_hw_fill_cap_info()
2514 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) { in ath9k_hw_fill_cap_info()
2516 return -EINVAL; in ath9k_hw_fill_cap_info()
2525 pCap->chip_chainmask = 1; in ath9k_hw_fill_cap_info()
2527 pCap->chip_chainmask = 7; in ath9k_hw_fill_cap_info()
2532 pCap->chip_chainmask = 3; in ath9k_hw_fill_cap_info()
2534 pCap->chip_chainmask = 7; in ath9k_hw_fill_cap_info()
2536 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); in ath9k_hw_fill_cap_info()
2541 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && in ath9k_hw_fill_cap_info()
2545 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; in ath9k_hw_fill_cap_info()
2547 pCap->rx_chainmask = 0x7; in ath9k_hw_fill_cap_info()
2550 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); in ath9k_hw_fill_cap_info()
2552 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask); in ath9k_hw_fill_cap_info()
2553 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask); in ath9k_hw_fill_cap_info()
2554 ah->txchainmask = pCap->tx_chainmask; in ath9k_hw_fill_cap_info()
2555 ah->rxchainmask = pCap->rx_chainmask; in ath9k_hw_fill_cap_info()
2557 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; in ath9k_hw_fill_cap_info()
2561 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; in ath9k_hw_fill_cap_info()
2563 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; in ath9k_hw_fill_cap_info()
2565 if (ah->hw_version.devid != AR2427_DEVID_PCIE) in ath9k_hw_fill_cap_info()
2566 pCap->hw_caps |= ATH9K_HW_CAP_HT; in ath9k_hw_fill_cap_info()
2568 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; in ath9k_hw_fill_cap_info()
2571 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; in ath9k_hw_fill_cap_info()
2573 pCap->rts_aggr_limit = (8 * 1024); in ath9k_hw_fill_cap_info()
2576 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); in ath9k_hw_fill_cap_info()
2577 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { in ath9k_hw_fill_cap_info()
2578 ah->rfkill_gpio = in ath9k_hw_fill_cap_info()
2579 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); in ath9k_hw_fill_cap_info()
2580 ah->rfkill_polarity = in ath9k_hw_fill_cap_info()
2581 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); in ath9k_hw_fill_cap_info()
2583 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; in ath9k_hw_fill_cap_info()
2587 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; in ath9k_hw_fill_cap_info()
2589 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; in ath9k_hw_fill_cap_info()
2592 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; in ath9k_hw_fill_cap_info()
2594 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; in ath9k_hw_fill_cap_info()
2597 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; in ath9k_hw_fill_cap_info()
2600 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; in ath9k_hw_fill_cap_info()
2602 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; in ath9k_hw_fill_cap_info()
2603 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; in ath9k_hw_fill_cap_info()
2604 pCap->rx_status_len = sizeof(struct ar9003_rxs); in ath9k_hw_fill_cap_info()
2605 pCap->tx_desc_len = sizeof(struct ar9003_txc); in ath9k_hw_fill_cap_info()
2606 pCap->txs_len = sizeof(struct ar9003_txs); in ath9k_hw_fill_cap_info()
2608 pCap->tx_desc_len = sizeof(struct ath_desc); in ath9k_hw_fill_cap_info()
2610 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; in ath9k_hw_fill_cap_info()
2614 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; in ath9k_hw_fill_cap_info()
2617 ah->ent_mode = 0x3BDA000; in ath9k_hw_fill_cap_info()
2619 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); in ath9k_hw_fill_cap_info()
2622 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; in ath9k_hw_fill_cap_info()
2625 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { in ath9k_hw_fill_cap_info()
2627 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); in ath9k_hw_fill_cap_info()
2629 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; in ath9k_hw_fill_cap_info()
2636 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) in ath9k_hw_fill_cap_info()
2637 pCap->hw_caps |= ATH9K_HW_CAP_APM; in ath9k_hw_fill_cap_info()
2641 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); in ath9k_hw_fill_cap_info()
2643 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; in ath9k_hw_fill_cap_info()
2649 pCap->hw_caps |= ATH9K_HW_CAP_DFS; in ath9k_hw_fill_cap_info()
2651 tx_chainmask = pCap->tx_chainmask; in ath9k_hw_fill_cap_info()
2652 rx_chainmask = pCap->rx_chainmask; in ath9k_hw_fill_cap_info()
2655 pCap->max_txchains++; in ath9k_hw_fill_cap_info()
2657 pCap->max_rxchains++; in ath9k_hw_fill_cap_info()
2664 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) in ath9k_hw_fill_cap_info()
2665 pCap->hw_caps |= ATH9K_HW_CAP_MCI; in ath9k_hw_fill_cap_info()
2668 pCap->hw_caps |= ATH9K_HW_CAP_RTT; in ath9k_hw_fill_cap_info()
2672 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) in ath9k_hw_fill_cap_info()
2673 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; in ath9k_hw_fill_cap_info()
2677 ah->wow.max_patterns = MAX_NUM_PATTERN; in ath9k_hw_fill_cap_info()
2679 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY; in ath9k_hw_fill_cap_info()
2723 if (ah->caps.gpio_requested & BIT(gpio)) in ath9k_hw_gpio_cfg_soc()
2726 err = devm_gpio_request_one(ah->dev, gpio, out ? GPIOF_OUT_INIT_LOW : GPIOF_IN, label); in ath9k_hw_gpio_cfg_soc()
2733 ah->caps.gpio_requested |= BIT(gpio); in ath9k_hw_gpio_cfg_soc()
2765 WARN_ON(gpio >= ah->caps.num_gpio_pins); in ath9k_hw_gpio_request()
2767 if (BIT(gpio) & ah->caps.gpio_mask) in ath9k_hw_gpio_request()
2793 WARN_ON(gpio >= ah->caps.num_gpio_pins); in ath9k_hw_gpio_free()
2795 if (ah->caps.gpio_requested & BIT(gpio)) in ath9k_hw_gpio_free()
2796 ah->caps.gpio_requested &= ~BIT(gpio); in ath9k_hw_gpio_free()
2807 WARN_ON(gpio >= ah->caps.num_gpio_pins); in ath9k_hw_gpio_get()
2809 if (BIT(gpio) & ah->caps.gpio_mask) { in ath9k_hw_gpio_get()
2824 } else if (BIT(gpio) & ah->caps.gpio_requested) { in ath9k_hw_gpio_get()
2836 WARN_ON(gpio >= ah->caps.num_gpio_pins); in ath9k_hw_set_gpio()
2843 if (BIT(gpio) & ah->caps.gpio_mask) { in ath9k_hw_set_gpio()
2848 } else if (BIT(gpio) & ah->caps.gpio_requested) { in ath9k_hw_set_gpio()
2913 ah->htc_reset_init = true; in ath9k_hw_phy_disable()
2940 return ah->eep_ops->get_eeprom(ah, gain_param); in get_antenna_gain()
2947 struct ieee80211_channel *channel; in ath9k_hw_apply_txpower() local
2957 channel = chan->chan; in ath9k_hw_apply_txpower()
2958 chan_pwr = min_t(int, channel->max_power * 2, MAX_COMBINED_POWER); in ath9k_hw_apply_txpower()
2959 new_pwr = min_t(int, chan_pwr, reg->power_limit); in ath9k_hw_apply_txpower()
2961 ah->eep_ops->set_txpower(ah, chan, ctl, in ath9k_hw_apply_txpower()
2968 struct ath9k_channel *chan = ah->curchan; in ath9k_hw_set_txpowerlimit()
2969 struct ieee80211_channel *channel = chan->chan; in ath9k_hw_set_txpowerlimit() local
2971 reg->power_limit = min_t(u32, limit, MAX_COMBINED_POWER); in ath9k_hw_set_txpowerlimit()
2973 channel->max_power = MAX_COMBINED_POWER / 2; in ath9k_hw_set_txpowerlimit()
2978 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); in ath9k_hw_set_txpowerlimit()
2984 ath9k_hw_set_operating_mode(ah, ah->opmode); in ath9k_hw_setopmode()
2999 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); in ath9k_hw_write_associd()
3000 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | in ath9k_hw_write_associd()
3001 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); in ath9k_hw_write_associd()
3048 ah->misc_mode |= AR_PCU_TX_ADD_TSF; in ath9k_hw_set_tsfadjust()
3050 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; in ath9k_hw_set_tsfadjust()
3058 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca) in ath9k_hw_set11nmac2040()
3105 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath9k_hw_gen_timer_start_tsf2()
3107 if (timer_table->tsf2_enabled) { in ath9k_hw_gen_timer_start_tsf2()
3119 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath_gen_timer_alloc()
3135 timer_table->timers[timer_index] = timer; in ath_gen_timer_alloc()
3136 timer->index = timer_index; in ath_gen_timer_alloc()
3137 timer->trigger = trigger; in ath_gen_timer_alloc()
3138 timer->overflow = overflow; in ath_gen_timer_alloc()
3139 timer->arg = arg; in ath_gen_timer_alloc()
3141 if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) { in ath_gen_timer_alloc()
3142 timer_table->tsf2_enabled = true; in ath_gen_timer_alloc()
3155 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath9k_hw_gen_timer_start()
3158 timer_table->timer_mask |= BIT(timer->index); in ath9k_hw_gen_timer_start()
3163 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, in ath9k_hw_gen_timer_start()
3165 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, in ath9k_hw_gen_timer_start()
3167 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, in ath9k_hw_gen_timer_start()
3168 gen_tmr_configuration[timer->index].mode_mask); in ath9k_hw_gen_timer_start()
3173 * to use. But we still follow the old rule, 0 - 7 use tsf and in ath9k_hw_gen_timer_start()
3174 * 8 - 15 use tsf2. in ath9k_hw_gen_timer_start()
3176 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) in ath9k_hw_gen_timer_start()
3178 (1 << timer->index)); in ath9k_hw_gen_timer_start()
3181 (1 << timer->index)); in ath9k_hw_gen_timer_start()
3184 if (timer->trigger) in ath9k_hw_gen_timer_start()
3185 mask |= SM(AR_GENTMR_BIT(timer->index), in ath9k_hw_gen_timer_start()
3187 if (timer->overflow) in ath9k_hw_gen_timer_start()
3188 mask |= SM(AR_GENTMR_BIT(timer->index), in ath9k_hw_gen_timer_start()
3193 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { in ath9k_hw_gen_timer_start()
3194 ah->imask |= ATH9K_INT_GENTIMER; in ath9k_hw_gen_timer_start()
3202 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath9k_hw_gen_timer_stop()
3205 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, in ath9k_hw_gen_timer_stop()
3206 gen_tmr_configuration[timer->index].mode_mask); in ath9k_hw_gen_timer_stop()
3212 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) { in ath9k_hw_gen_timer_stop()
3214 (1 << timer->index)); in ath9k_hw_gen_timer_stop()
3220 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | in ath9k_hw_gen_timer_stop()
3221 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); in ath9k_hw_gen_timer_stop()
3223 timer_table->timer_mask &= ~BIT(timer->index); in ath9k_hw_gen_timer_stop()
3225 if (timer_table->timer_mask == 0) { in ath9k_hw_gen_timer_stop()
3226 ah->imask &= ~ATH9K_INT_GENTIMER; in ath9k_hw_gen_timer_stop()
3234 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath_gen_timer_free()
3237 timer_table->timers[timer->index] = NULL; in ath_gen_timer_free()
3247 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath_gen_timer_isr()
3253 trigger_mask = ah->intr_gen_timer_trigger; in ath_gen_timer_isr()
3254 thresh_mask = ah->intr_gen_timer_thresh; in ath_gen_timer_isr()
3255 trigger_mask &= timer_table->timer_mask; in ath_gen_timer_isr()
3256 thresh_mask &= timer_table->timer_mask; in ath_gen_timer_isr()
3258 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) { in ath_gen_timer_isr()
3259 timer = timer_table->timers[index]; in ath_gen_timer_isr()
3262 if (!timer->overflow) in ath_gen_timer_isr()
3266 timer->overflow(timer->arg); in ath_gen_timer_isr()
3269 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) { in ath_gen_timer_isr()
3270 timer = timer_table->timers[index]; in ath_gen_timer_isr()
3273 if (!timer->trigger) in ath_gen_timer_isr()
3275 timer->trigger(timer->arg); in ath_gen_timer_isr()
3293 /* Single-chip solutions */
3358 /* chipsets >= AR9280 are single-chip */ in ath9k_hw_name()
3362 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), in ath9k_hw_name()
3363 ah->hw_version.macRev); in ath9k_hw_name()
3368 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), in ath9k_hw_name()
3369 ah->hw_version.macRev, in ath9k_hw_name()
3370 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev in ath9k_hw_name()
3372 ah->hw_version.phyRev); in ath9k_hw_name()