Lines Matching +full:0 +full:xae0

38 #define AR5416_EEPROM_MAGIC 0x5aa5
40 #define AR5416_EEPROM_MAGIC 0xa55a
43 #define CTRY_DEBUG 0x1ff
44 #define CTRY_DEFAULT 0
46 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
47 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
48 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
49 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
50 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
52 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
53 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
56 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
57 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
58 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
59 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
60 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
61 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
63 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
64 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
66 #define AR5416_EEPROM_MAGIC_OFFSET 0x0
68 #define AR5416_EEPROM_OFFSET 0x2000
69 #define AR5416_EEPROM_MAX 0xae0
72 (AR_SREV_9100(_ah)) ? 0x1fff1000 : 0x503f1200
74 #define SD_NO_CTL 0xE0
75 #define NO_CTL 0xff
76 #define CTL_MODE_M 0xf
77 #define CTL_11A 0
85 #define EXT_ADDITIVE (0x8000)
100 * Bit 0: en_fcc_mid
106 #define AR9285_RDEXT_DEFAULT 0x1F
108 #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
118 #define EEP_RFSILENT_ENABLED 0x0001
119 #define EEP_RFSILENT_ENABLED_S 0
120 #define EEP_RFSILENT_POLARITY 0x0002
122 #define EEP_RFSILENT_GPIO_SEL ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00fc : 0x001c)
125 #define AR5416_OPFLAGS_11A 0x01
126 #define AR5416_OPFLAGS_11G 0x02
127 #define AR5416_OPFLAGS_N_5G_HT40 0x04
128 #define AR5416_OPFLAGS_N_2G_HT40 0x08
129 #define AR5416_OPFLAGS_N_5G_HT20 0x10
130 #define AR5416_OPFLAGS_N_2G_HT20 0x20
132 #define AR5416_EEP_NO_BACK_VER 0x1
133 #define AR5416_EEP_VER 0xE
135 #define AR5416_EEP_VER_MAJOR_MASK 0xF000
136 #define AR5416_EEP_VER_MINOR_MASK 0x0FFF
137 #define AR5416_EEP_MINOR_VER_2 0x2
138 #define AR5416_EEP_MINOR_VER_3 0x3
139 #define AR5416_EEP_MINOR_VER_7 0x7
140 #define AR5416_EEP_MINOR_VER_9 0x9
141 #define AR5416_EEP_MINOR_VER_16 0x10
142 #define AR5416_EEP_MINOR_VER_17 0x11
143 #define AR5416_EEP_MINOR_VER_19 0x13
144 #define AR5416_EEP_MINOR_VER_20 0x14
145 #define AR5416_EEP_MINOR_VER_21 0x15
146 #define AR5416_EEP_MINOR_VER_22 0x16
161 #define AR5416_BCHAN_UNUSED 0xFF
168 #define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
173 #define AR5416_EEP_TXGAIN_ORIGINAL 0
177 #define AR5416_EEPMISC_BIG_ENDIAN 0x01
191 #define AR9287_EEP_VER 0xE
192 #define AR9287_EEP_MINOR_VER_1 0x1
193 #define AR9287_EEP_MINOR_VER_2 0x2
194 #define AR9287_EEP_MINOR_VER_3 0x3
208 #define AR9287_EEPMISC_WOW 0x02
218 #define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f)
219 #define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03)
221 #define LNA_CTL_BUF_MODE BIT(0)
279 ATH9K_HAL_FREQ_BAND_5GHZ = 0,
448 #define EEP_4K_BB_DESIRED_SCALE_MASK 0x1f
638 REG_EXT_FCC_MIDBAND = 0,