829 		idx = 0;  in ar9003_tx_gain_table_apply()
980 	case 0:  in ar9003_rx_gain_table_apply()
1025 		if ((val & 0xff000000) == 0x17000000) {  in ar9003_hw_configpcipowersave()
1026 			val &= 0x00ffffff;  in ar9003_hw_configpcipowersave()
1027 			val |= 0x27000000;  in ar9003_hw_configpcipowersave()
1028 			REG_WRITE(ah, 0x570c, val);  in ar9003_hw_configpcipowersave()
1046 	for (i = 0; i < array->ia_rows; i++) {  in ar9003_hw_configpcipowersave()
1048 			  INI_RA(array, i, 0),  in ar9003_hw_configpcipowersave()
1077  * Signature: dcu_chain_state is 0x6 and dcu_complete_state is 0x1.
1082  * Chain 0 state : Bits 4:0   of AR_DMADBG_4
1088  * Chain 6 state : Bits 4:0   of AR_DMADBG_5
1093  * The DCU chain state "0x6" means "WAIT_FRDONE" - wait for TX frame to be done.
1113 	for (i = 0; i < NUM_STATUS_READS; i++) {  in ath9k_hw_verify_hang()
1117 		dcu_chain_state = (dma_dbg_chain >> reg_offset) & 0x1f;  in ath9k_hw_verify_hang()
1118 		dcu_complete_state = dma_dbg_complete & 0x3;  in ath9k_hw_verify_hang()
1120 		if ((dcu_chain_state != 0x6) || (dcu_complete_state != 0x1))  in ath9k_hw_verify_hang()
1135 	unsigned long chk_dcu = 0;  in ar9003_hw_detect_mac_hang()
1137 	unsigned int i = 0;  in ar9003_hw_detect_mac_hang()
1143 	dcu_complete_state = dma_dbg_6 & 0x3;  in ar9003_hw_detect_mac_hang()
1144 	if (dcu_complete_state != 0x1)  in ar9003_hw_detect_mac_hang()
1147 	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {  in ar9003_hw_detect_mac_hang()
1156 		dcu_chain_state = (chk_dbg >> reg_offset) & 0x1f;  in ar9003_hw_detect_mac_hang()
1157 		if (dcu_chain_state == 0x6) {  in ar9003_hw_detect_mac_hang()
1163 	if ((dcu_complete_state == 0x1) && dcu_wait_frdone) {  in ar9003_hw_detect_mac_hang()