Lines Matching +full:rom +full:- +full:addr
2 * Copyright (c) 2004-2011 Atheros Communications Inc.
37 * command-specific data.
45 * BMI handles all required Target-side cache flushing.
104 * Semantics: Read a 32-bit Target SOC register.
114 * Semantics: Write a 32-bit Target SOC register.
126 * Semantics: Fetch the 4-byte Target information
141 * Semantics: Install a ROM Patch.
144 * u32 Target ROM Address
147 * u32 Activate? 1-->activate;
148 * 0-->install but do not activate
155 * Semantics: Uninstall a previously-installed ROM Patch,
166 * Semantics: Activate a list of previously-installed ROM Patches.
177 * Semantics: Deactivate a list of active ROM Patches.
189 * Semantics: Begin an LZ-compressed stream of input
198 * Note: Not supported on all versions of ROM firmware.
203 * Semantics: Host writes ATH6KL memory with LZ-compressed
214 * Note: Not supported on all versions of ROM firmware.
228 u32 addr; \
231 addr = ath6kl_get_hi_item_addr(ar, HI_ITEM(item)); \
233 ath6kl_bmi_write(ar, addr, (u8 *) &v, sizeof(v)); \
238 u32 addr, *check_type = val; \
243 addr = ath6kl_get_hi_item_addr(ar, HI_ITEM(item)); \
244 ret = ath6kl_bmi_read(ar, addr, (u8 *) &tmp, 4); \
257 int ath6kl_bmi_read(struct ath6kl *ar, u32 addr, u8 *buf, u32 len);
258 int ath6kl_bmi_write(struct ath6kl *ar, u32 addr, u8 *buf, u32 len);
260 u32 addr, u32 *param);
262 u32 addr);
263 int ath6kl_bmi_reg_read(struct ath6kl *ar, u32 addr, u32 *param);
264 int ath6kl_bmi_reg_write(struct ath6kl *ar, u32 addr, u32 param);
268 u32 addr);
270 u32 addr, u8 *buf, u32 len);