Lines Matching full:cbr
187 #define AR5K_TXCFG_RDY_CBR_DIS 0x00004000 /* Ready time CBR disable [5211+] */
325 #define AR5K_ISR_QCBRORN 0x02000000 /* QCU CBR overrun [5211+] */
326 #define AR5K_ISR_QCBRURN 0x04000000 /* QCU CBR underrun [5211+] */
425 #define AR5K_IMR_QCBRORN 0x02000000 /* QCU CBR overrun (?) [5211+] */
426 #define AR5K_IMR_QCBRURN 0x04000000 /* QCU CBR underrun (?) [5211+] */
547 * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate)
588 #define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff /* CBR Interval mask */
590 #define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000 /* CBR overrun threshold mask */
626 #define AR5K_QCU_MISC_CBREXP_DIS 0x00000020 /* Disable CBR expired counter (normal queue) */
627 #define AR5K_QCU_MISC_CBREXP_BCN_DIS 0x00000040 /* Disable CBR expired counter (beacon queue) */
629 #define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /* CBR expired threshold enabled */
631 #define AR5K_QCU_MISC_CBR_RESET_CNT 0x00000400 /* CBR threshold (counter) reset */
642 #define AR5K_QCU_STS_CBREXPCNT 0x0000ff00 /* CBR expired counter */