Lines Matching +full:txpower +full:- +full:5 +full:g
2 * Copyright (c) 2004-2008 Reyk Floeter <[email protected]>
3 * Copyright (c) 2006-2008 Nick Kossifidis <[email protected]>
22 #define AR5K_EEPROM_PCIE_OFFSET 0x02 /* Contains offset to PCI-E infos */
26 #define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 /* Default - found on EEPROM */
39 #define AR5K_EEPROM_SIZE_LOWER 0x1b /* size info -- lower */
40 #define AR5K_EEPROM_SIZE_UPPER 0x1c /* size info -- upper */
47 #define AR5K_EEPROM_INFO_MAX (0x400 - AR5K_EEPROM_INFO_BASE)
82 #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) /* Disable turbo for 5GHz */
99 #define AR5K_EEPROM_MISC1 AR5K_EEPROM_INFO(5)
114 #define AR5K_EEPROM_MASK_R0(_v) (((_v) >> 2) & 0x3) /* modes supported by radio 0 (bit 1: G, bit 2…
115 #define AR5K_EEPROM_MASK_R1(_v) ((_v) & 0x3) /* modes supported by radio 1 (bit 1: G, bit 2: A) */
129 #define AR5K_EEPROM_FCC_MID_EN (((_v) >> 6) & 0x1) /* 5.47-5.7GHz supported */
130 #define AR5K_EEPROM_JAP_U1EVEN_EN (((_v) >> 7) & 0x1) /* Japan UNII1 band (5.15-5.25GHz) on even ch…
131 #define AR5K_EEPROM_JAP_U2_EN (((_v) >> 8) & 0x1) /* Japan UNII2 band (5.25-5.35GHz) supported */
132 #define AR5K_EEPROM_JAP_MID_EN (((_v) >> 9) & 0x1) /* Japan band from 5.47-5.7GHz supported */
133 #define AR5K_EEPROM_JAP_U1ODD_EN (((_v) >> 10) & 0x1) /* Japan UNII2 band (5.15-5.25GHz) on odd cha…
158 /* [3.1 - 3.3] */
163 #define AR5K_EEPROM_PROTECT_RD_0_31 0x0001 /* Read protection bit for offsets 0x0 - 0x1f */
164 #define AR5K_EEPROM_PROTECT_WR_0_31 0x0002 /* Write protection bit for offsets 0x0 - 0x1f */
165 #define AR5K_EEPROM_PROTECT_RD_32_63 0x0004 /* 0x20 - 0x3f */
167 #define AR5K_EEPROM_PROTECT_RD_64_127 0x0010 /* 0x40 - 0x7f */
169 #define AR5K_EEPROM_PROTECT_RD_128_191 0x0040 /* 0x80 - 0xbf (regdom) */
171 #define AR5K_EEPROM_PROTECT_RD_192_207 0x0100 /* 0xc0 - 0xcf */
173 #define AR5K_EEPROM_PROTECT_RD_208_223 0x0400 /* 0xd0 - 0xdf */
175 #define AR5K_EEPROM_PROTECT_RD_224_239 0x1000 /* 0xe0 - 0xef */
177 #define AR5K_EEPROM_PROTECT_RD_240_255 0x4000 /* 0xf0 - 0xff */
192 #define AR5K_EEPROM_N_PHASE_CAL 5
213 #define AR5K_EEPROM_N_PD_POINTS 5
226 /* 5GHz/2GHz */
233 #define AR5K_EEPROM_N_SPUR_CHANS 5
246 return -EIO; \
250 AR5K_EEPROM_READ(_o, ah->ah_capabilities.cap_eeprom._v); \
265 AR5K_CTL_2GHT20 = 5,
337 * gain to higher gain (max txpower -> min txpower) */
346 /* Power level for 6-24Mbit/s rates or
368 * struct ath5k_eeprom_info - EEPROM calibration data
376 * (11Mbps) rate in G mode. 0.1dB steps
386 * B/G mode: Index [0] is used for AR2112/5112, otherwise [1]
387 * A mode: [0] 5.15-5.25 [1] 5.25-5.50 [2] 5.50-5.70 [3] 5.70-5.85 GHz
463 /* Back mapping pdcurve number -> pdcurve index in pd->pd_curves */