Lines Matching +full:a +full:- +full:bit
1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
27 #define RX_MPDU_START_INFO0_FLOW_ID_TOEPLITZ BIT(7)
28 #define RX_MPDU_START_INFO0_PKT_SEL_FP_UCAST_DATA BIT(8)
29 #define RX_MPDU_START_INFO0_PKT_SEL_FP_MCAST_DATA BIT(9)
30 #define RX_MPDU_START_INFO0_PKT_SEL_FP_CTRL_BAR BIT(10)
33 #define RX_MPDU_START_INFO0_MCAST_ECHO_DROP_EN BIT(17)
34 #define RX_MPDU_START_INFO0_WDS_LEARN_DETECT_EN BIT(18)
35 #define RX_MPDU_START_INFO0_INTRA_BSS_CHECK_EN BIT(19)
36 #define RX_MPDU_START_INFO0_USE_PPE BIT(20)
37 #define RX_MPDU_START_INFO0_PPE_ROUTING_EN BIT(21)
41 #define RX_MPDU_START_INFO1_PRE_DELIM_ERR_WARN BIT(24)
42 #define RX_MPDU_START_INFO1_FIRST_DELIM_ERR BIT(25)
44 #define RX_MPDU_START_INFO2_EPD_EN BIT(0)
45 #define RX_MPDU_START_INFO2_ALL_FRAME_ENCPD BIT(1)
49 #define RX_MPDU_START_INFO2_BSSID_HIT BIT(10)
55 #define RX_MPDU_START_INFO3_NDP_FRAME BIT(9)
56 #define RX_MPDU_START_INFO3_PHY_ERR BIT(10)
57 #define RX_MPDU_START_INFO3_PHY_ERR_MPDU_HDR BIT(11)
58 #define RX_MPDU_START_INFO3_PROTO_VER_ERR BIT(12)
59 #define RX_MPDU_START_INFO3_AST_LOOKUP_VALID BIT(13)
60 #define RX_MPDU_START_INFO3_RANGING BIT(14)
62 #define RX_MPDU_START_INFO4_MPDU_FCTRL_VALID BIT(0)
63 #define RX_MPDU_START_INFO4_MPDU_DUR_VALID BIT(1)
64 #define RX_MPDU_START_INFO4_MAC_ADDR1_VALID BIT(2)
65 #define RX_MPDU_START_INFO4_MAC_ADDR2_VALID BIT(3)
66 #define RX_MPDU_START_INFO4_MAC_ADDR3_VALID BIT(4)
67 #define RX_MPDU_START_INFO4_MAC_ADDR4_VALID BIT(5)
68 #define RX_MPDU_START_INFO4_MPDU_SEQ_CTRL_VALID BIT(6)
69 #define RX_MPDU_START_INFO4_MPDU_QOS_CTRL_VALID BIT(7)
70 #define RX_MPDU_START_INFO4_MPDU_HT_CTRL_VALID BIT(8)
71 #define RX_MPDU_START_INFO4_ENCRYPT_INFO_VALID BIT(9)
73 #define RX_MPDU_START_INFO4_MORE_FRAG_FLAG BIT(14)
74 #define RX_MPDU_START_INFO4_FROM_DS BIT(16)
75 #define RX_MPDU_START_INFO4_TO_DS BIT(17)
76 #define RX_MPDU_START_INFO4_ENCRYPTED BIT(18)
77 #define RX_MPDU_START_INFO4_MPDU_RETRY BIT(19)
81 #define RX_MPDU_START_INFO5_NEW_PEER_ENTRY BIT(8)
82 #define RX_MPDU_START_INFO5_DECRYPT_NEEDED BIT(9)
84 #define RX_MPDU_START_INFO5_VLAN_TAG_C_PADDING BIT(12)
85 #define RX_MPDU_START_INFO5_VLAN_TAG_S_PADDING BIT(13)
86 #define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_C BIT(14)
87 #define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_S BIT(15)
89 #define RX_MPDU_START_INFO5_AMPDU_FLAG BIT(28)
90 #define RX_MPDU_START_INFO5_BAR_FRAME BIT(29)
91 #define RX_MPDU_START_INFO5_RAW_MPDU BIT(30)
94 #define RX_MPDU_START_INFO6_FIRST_MPDU BIT(14)
95 #define RX_MPDU_START_INFO6_MCAST_BCAST BIT(15)
96 #define RX_MPDU_START_INFO6_AST_IDX_NOT_FOUND BIT(16)
97 #define RX_MPDU_START_INFO6_AST_IDX_TIMEOUT BIT(17)
98 #define RX_MPDU_START_INFO6_POWER_MGMT BIT(18)
99 #define RX_MPDU_START_INFO6_NON_QOS BIT(19)
100 #define RX_MPDU_START_INFO6_NULL_DATA BIT(20)
101 #define RX_MPDU_START_INFO6_MGMT_TYPE BIT(21)
102 #define RX_MPDU_START_INFO6_CTRL_TYPE BIT(22)
103 #define RX_MPDU_START_INFO6_MORE_DATA BIT(23)
104 #define RX_MPDU_START_INFO6_EOSP BIT(24)
105 #define RX_MPDU_START_INFO6_FRAGMENT BIT(25)
106 #define RX_MPDU_START_INFO6_ORDER BIT(26)
107 #define RX_MPDU_START_INFO6_UAPSD_TRIGGER BIT(27)
108 #define RX_MPDU_START_INFO6_ENCRYPT_REQUIRED BIT(28)
109 #define RX_MPDU_START_INFO6_DIRECTED BIT(29)
110 #define RX_MPDU_START_INFO6_AMSDU_PRESENT BIT(30)
114 #define RX_MPDU_START_INFO7_PRIORITY_VALID BIT(17)
117 #define RX_MPDU_START_INFO8_AUTH_TO_SEND_WDS BIT(0)
150 #define QCN9274_MPDU_START_SELECT_MPDU_START_TAG BIT(0)
151 #define QCN9274_MPDU_START_SELECT_INFO0_REO_QUEUE_DESC_LO BIT(1)
152 #define QCN9274_MPDU_START_SELECT_INFO1_PN_31_0 BIT(2)
153 #define QCN9274_MPDU_START_SELECT_PN_95_32 BIT(3)
154 #define QCN9274_MPDU_START_SELECT_PN_127_96_INFO2 BIT(4)
155 #define QCN9274_MPDU_START_SELECT_PEER_MDATA_INFO3_PHY_PPDU_ID BIT(5)
156 #define QCN9274_MPDU_START_SELECT_AST_IDX_SW_PEER_ID_INFO4 BIT(6)
157 #define QCN9274_MPDU_START_SELECT_INFO5_INFO6 BIT(7)
158 #define QCN9274_MPDU_START_SELECT_FRAME_CTRL_DURATION_ADDR1_31_0 BIT(8)
159 #define QCN9274_MPDU_START_SELECT_ADDR2_47_0_ADDR1_47_32 BIT(9)
160 #define QCN9274_MPDU_START_SELECT_ADDR3_47_0_SEQ_CTRL BIT(10)
161 #define QCN9274_MPDU_START_SELECT_ADDR4_47_0_QOS_CTRL BIT(11)
162 #define QCN9274_MPDU_START_SELECT_HT_CTRL_INFO7 BIT(12)
163 #define QCN9274_MPDU_START_SELECT_ML_ADDR1_47_0_ML_ADDR2_15_0 BIT(13)
164 #define QCN9274_MPDU_START_SELECT_ML_ADDR2_47_16_INFO8 BIT(14)
165 #define QCN9274_MPDU_START_SELECT_RES_0_RES_1 BIT(15)
215 * is 2'b00, Rx OLE uses a REO destination indicati'n of {1'b1,
219 * 's not 2'b00, Rx OLE uses a REO destination indication of
242 * pkt_selection_fp_... bit is set
246 * pkt_selection_fp_... bit is set
257 * field in address search failure cache-only entry should
261 * If set, intra-BSS routing detection is enabled
265 * and use a programmed value corresponding to the REO2PPE
275 * Global enable/disable bit for routing to PPE, used to disable
277 * This is set by SW for peers which are being handled by a
279 * buffer management for WiFi-to-PPE routing.
282 * by a different subsystem, completely disabling WiFi-to-PPE
296 * Indicates that a delimiter FCS error was found in between the
297 * previous MPDU and this MPDU. Note that this is just a warning,
303 * Indicates that the first delimiter had a FCS failure.
365 * When set, a PHY error was received before MAC received any
369 * When set, a PHY error was received before MAC received the
373 * Set when RXPCU detected a version error in the Frame control
377 * When set, AST based lookup for this frame has found a valid
381 * When set, a ranging NDPA or a ranging NDP was received.
384 * A ppdu counter value that PHY increments for every PPDU
392 * A value of 0xFFFF indicates an invalid AST index, meaning
398 * This field indicates a unique peer identifier. It is set
414 * For MPDUs without a sequence control field, this field will
420 * information, For MPDUs without a QoS,HT control field, this field
436 * The More Fragment bit setting from the MPDU header of the
442 * Set if the from DS bit is set in the frame control.
447 * Set if the to DS bit is set in the frame control.
452 * Protected bit from the frame control.
456 * Retry bit from the frame control. Only valid when first_msdu is set
472 * When RXPCU sets bit 'ast_index_not_found or ast_index_timeout',
473 * RXPCU will also ensure that this bit is NOT set. CRYPTO for that
474 * reason only needs to evaluate this bit and non of the other ones
492 * received MPDU in the PPDU and this MPDU gets filtered-in,
501 * Received frame was part of an A-MPDU.
504 * Received frame is a BAR frame
514 * and last_mpdu are set in the MSDU then this is a not an
515 * A-MPDU frame but a stand alone MPDU. Interior MPDU in an
516 * A-MPDU shall have both first_mpdu and last_mpdu bits set to
517 * 0. The PPDU start status will only be valid when this bit
522 * address 1 bit 0 is set indicating mcast/bcast and the BSSID
535 * Power management bit set in the 802.11 header. Only set
539 * Set if packet is not a non-QoS data frame. Only set when
547 * Set if packet is a management packet. Only set when
551 * Set if packet is a control packet. Only set when first_msdu
555 * Set if more bit in frame control is set. Only set when
559 * Set if the EOSP (end of service period) bit in the QoS
567 * Set if the order bit in the frame control is set. Only
571 * U-APSD trigger frame
579 * MPDU is a directed packet which means that the RA matched
582 * 'no_ack' bit is the address search entry cleared.
594 * address valid bit is set
602 * RXOLE uses this to determine intra-BSS routing.
605 * Opaque service code between PPE and Wi-Fi
621 * data frames to multi-link addresses during decapsulation to eth/nwifi
624 * Multi-link receiver address1,2. Only valid when corresponding
625 * valid bit is set
628 * If not set, RXDMA shall perform error-routing for WDS packets
674 #define RX_MSDU_END_INFO2_CCND_TRUNCATE BIT(14)
675 #define RX_MSDU_END_INFO2_CCND_CCE_DIS BIT(15)
679 #define RX_MSDU_END_INFO3_DA_OFFSET_VALID BIT(12)
680 #define RX_MSDU_END_INFO3_SA_OFFSET_VALID BIT(13)
683 #define RX_MSDU_END_INFO4_LRO_ELIGIBLE BIT(9)
685 #define RX_MSDU_END_INFO5_SA_IDX_TIMEOUT BIT(0)
686 #define RX_MSDU_END_INFO5_DA_IDX_TIMEOUT BIT(1)
687 #define RX_MSDU_END_INFO5_TO_DS BIT(2)
689 #define RX_MSDU_END_INFO5_SA_IS_VALID BIT(7)
690 #define RX_MSDU_END_INFO5_DA_IS_VALID BIT(8)
691 #define RX_MSDU_END_INFO5_DA_IS_MCBC BIT(9)
693 #define RX_MSDU_END_INFO5_FIRST_MSDU BIT(12)
694 #define RX_MSDU_END_INFO5_LAST_MSDU BIT(13)
695 #define RX_MSDU_END_INFO5_FROM_DS BIT(14)
696 #define RX_MSDU_END_INFO5_IP_CHKSUM_FAIL_COPY BIT(15)
698 #define RX_MSDU_END_INFO6_MSDU_DROP BIT(0)
701 #define RX_MSDU_END_INFO6_USE_PPE BIT(26)
703 #define RX_MSDU_END_INFO6_VLAN_CTAG_STRIPPED BIT(29)
704 #define RX_MSDU_END_INFO6_VLAN_STAG_STRIPPED BIT(30)
705 #define RX_MSDU_END_INFO6_FRAGMENT_FLAG BIT(31)
708 #define RX_MSDU_END_INFO7_FLOW_AGGR_CONTN BIT(8)
709 #define RX_MSDU_END_INFO7_FISA_TIMEOUT BIT(9)
711 #define RX_MSDU_END_INFO7_TCPUDP_CSUM_FAIL_CPY BIT(10)
712 #define RX_MSDU_END_INFO7_MSDU_LIMIT_ERROR BIT(11)
713 #define RX_MSDU_END_INFO7_FLOW_IDX_TIMEOUT BIT(12)
714 #define RX_MSDU_END_INFO7_FLOW_IDX_INVALID BIT(13)
715 #define RX_MSDU_END_INFO7_CCE_MATCH BIT(14)
716 #define RX_MSDU_END_INFO7_AMSDU_PARSER_ERR BIT(15)
721 #define RX_MSDU_END_INFO9_PRIORITY_VALID BIT(15)
722 #define RX_MSDU_END_INFO9_INRA_BSS BIT(16)
724 #define RX_MSDU_END_INFO9_MCAST_ECHO BIT(19)
725 #define RX_MSDU_END_INFO9_WDS_LEARN_EVENT BIT(20)
726 #define RX_MSDU_END_INFO9_WDS_ROAM_EVENT BIT(21)
727 #define RX_MSDU_END_INFO9_WDS_KEEP_ALIVE_EVENT BIT(22)
730 #define RX_MSDU_END_INFO10_STBC BIT(14)
731 #define RX_MSDU_END_INFO10_IPSEC_ESP BIT(15)
733 #define RX_MSDU_END_INFO10_IPSEC_AH BIT(23)
738 #define RX_MSDU_END_INFO11_IPV4 BIT(10)
739 #define RX_MSDU_END_INFO11_IPV6 BIT(11)
740 #define RX_MSDU_END_INFO11_TCP BIT(12)
741 #define RX_MSDU_END_INFO11_UDP BIT(13)
742 #define RX_MSDU_END_INFO11_IP_FRAG BIT(14)
743 #define RX_MSDU_END_INFO11_TCP_ONLY_ACK BIT(15)
744 #define RX_MSDU_END_INFO11_DA_IS_BCAST_MCAST BIT(16)
746 #define RX_MSDU_END_INFO11_IP_FIXED_HDR_VALID BIT(19)
747 #define RX_MSDU_END_INFO11_IP_EXTN_HDR_VALID BIT(20)
748 #define RX_MSDU_END_INFO11_IP_TCP_UDP_HDR_VALID BIT(21)
749 #define RX_MSDU_END_INFO11_MESH_CTRL_PRESENT BIT(22)
750 #define RX_MSDU_END_INFO11_LDPC BIT(23)
761 #define RX_MSDU_END_INFO12_MIMO_DONE_COPY BIT(31)
763 #define RX_MSDU_END_INFO13_FIRST_MPDU BIT(0)
764 #define RX_MSDU_END_INFO13_MCAST_BCAST BIT(2)
765 #define RX_MSDU_END_INFO13_AST_IDX_NOT_FOUND BIT(3)
766 #define RX_MSDU_END_INFO13_AST_IDX_TIMEDOUT BIT(4)
767 #define RX_MSDU_END_INFO13_POWER_MGMT BIT(5)
768 #define RX_MSDU_END_INFO13_NON_QOS BIT(6)
769 #define RX_MSDU_END_INFO13_NULL_DATA BIT(7)
770 #define RX_MSDU_END_INFO13_MGMT_TYPE BIT(8)
771 #define RX_MSDU_END_INFO13_CTRL_TYPE BIT(9)
772 #define RX_MSDU_END_INFO13_MORE_DATA BIT(10)
773 #define RX_MSDU_END_INFO13_EOSP BIT(11)
774 #define RX_MSDU_END_INFO13_A_MSDU_ERROR BIT(12)
775 #define RX_MSDU_END_INFO13_ORDER BIT(14)
776 #define RX_MSDU_END_INFO13_OVERFLOW_ERR BIT(16)
777 #define RX_MSDU_END_INFO13_MSDU_LEN_ERR BIT(17)
778 #define RX_MSDU_END_INFO13_TCP_UDP_CKSUM_FAIL BIT(18)
779 #define RX_MSDU_END_INFO13_IP_CKSUM_FAIL BIT(19)
780 #define RX_MSDU_END_INFO13_SA_IDX_INVALID BIT(20)
781 #define RX_MSDU_END_INFO13_DA_IDX_INVALID BIT(21)
782 #define RX_MSDU_END_INFO13_AMSDU_ADDR_MISMATCH BIT(22)
783 #define RX_MSDU_END_INFO13_RX_IN_TX_DECRYPT_BYP BIT(23)
784 #define RX_MSDU_END_INFO13_ENCRYPT_REQUIRED BIT(24)
785 #define RX_MSDU_END_INFO13_DIRECTED BIT(25)
786 #define RX_MSDU_END_INFO13_BUFFER_FRAGMENT BIT(26)
787 #define RX_MSDU_END_INFO13_MPDU_LEN_ERR BIT(27)
788 #define RX_MSDU_END_INFO13_TKIP_MIC_ERR BIT(28)
789 #define RX_MSDU_END_INFO13_DECRYPT_ERR BIT(29)
790 #define RX_MSDU_END_INFO13_UNDECRYPT_FRAME_ERR BIT(30)
791 #define RX_MSDU_END_INFO13_FCS_ERR BIT(31)
793 #define RX_MSDU_END_INFO13_WIFI_PARSER_ERR BIT(15)
796 #define RX_MSDU_END_INFO14_RX_BITMAP_NOT_UPDED BIT(13)
797 #define RX_MSDU_END_INFO14_MSDU_DONE BIT(31)
845 #define QCN9274_MSDU_END_SELECT_MSDU_END_TAG BIT(0)
846 #define QCN9274_MSDU_END_SELECT_INFO0_PHY_PPDUID_IP_HDR_CSUM_INFO1 BIT(1)
847 #define QCN9274_MSDU_END_SELECT_INFO2_CUMULATIVE_CSUM_RULE_IND_0 BIT(2)
848 #define QCN9274_MSDU_END_SELECT_IPV6_OP_CRC_INFO3_TYPE13 BIT(3)
849 #define QCN9274_MSDU_END_SELECT_RULE_IND_1_TCP_SEQ_NUM BIT(4)
850 #define QCN9274_MSDU_END_SELECT_TCP_ACK_NUM_INFO4_WINDOW_SIZE BIT(5)
851 #define QCN9274_MSDU_END_SELECT_SA_SW_PER_ID_INFO5_SA_DA_ID BIT(6)
852 #define QCN9274_MSDU_END_SELECT_INFO6_FSE_METADATA BIT(7)
853 #define QCN9274_MSDU_END_SELECT_CCE_MDATA_TCP_UDP_CSUM_INFO7_IP_LEN BIT(8)
854 #define QCN9274_MSDU_END_SELECT_INFO8_INFO9 BIT(9)
855 #define QCN9274_MSDU_END_SELECT_INFO10_INFO11 BIT(10)
856 #define QCN9274_MSDU_END_SELECT_VLAN_CTAG_STAG_CI_PEER_MDATA BIT(11)
857 #define QCN9274_MSDU_END_SELECT_INFO12_AND_FLOW_ID_TOEPLITZ BIT(12)
858 #define QCN9274_MSDU_END_SELECT_PPDU_START_TS_63_32_PHY_MDATA BIT(13)
859 #define QCN9274_MSDU_END_SELECT_PPDU_START_TS_31_0_TOEPLITZ_HASH_2_4 BIT(14)
860 #define QCN9274_MSDU_END_SELECT_RES0_SA_47_0 BIT(15)
861 #define QCN9274_MSDU_END_SELECT_INFO13_INFO14 BIT(16)
903 * A ppdu counter value that PHY increments for every PPDU
913 * A-MPDU delimiter or the preamble length field for non-A-MPDU
934 * 32 bit CRC computed out of IP v6 extension headers.
944 * of a dynamic A-MSDU when DA is compressed.
948 * of a dynamic A-MSDU when SA is compressed.
951 * The 16-bit type value indicating the type of L3 later
984 * Set if the to DS bit is set in the frame control.
990 * Indicates that OLE found a valid SA entry.
993 * Indicates that OLE found a valid DA entry.
997 * was a Multicast of Broadcast address.
1001 * always start of a Dword boundary.
1004 * Indicates the first MSDU of A-MSDU. If both first_msdu and
1005 * last_msdu are set in the MSDU then this is a non-aggregated MSDU
1006 * frame: normal MPDU. Interior MSDU in an A-MSDU shall have both
1010 * Indicates the last MSDU of the A-MSDU. MPDU end status is only
1014 * Set if the from DS bit is set in the frame control.
1025 * Based on a register configuration in RXOLE, this field will
1045 * and use a programmed value corresponding to the REO2PPE
1049 * When set, this is a Mesh (11s) STA.
1052 * Set by RXOLE if it stripped 4-bytes of C-VLAN Tag from the
1056 * Set by RXOLE if it stripped 4-bytes of S-VLAN Tag from the
1061 * set when either the more_frag bit is set in the frame control
1072 * The value of the computed TCP/UDP checksum. A mode bit
1094 * decapsulated but will be DMA'ed in RAW format as a single MSDU.
1104 * Indicates that this status has a corresponding MSDU that
1110 * A-MSDU could not be properly de-agregated.
1120 * Opaque service code between PPE and Wi-Fi
1126 * This packet needs intra-BSS routing by SW as the 'vdev_id'
1132 * to support intra-BSS routing with multi-chip multi-link
1137 * If set, this packet is a multicast echo, i.e. the DA is
1154 * than the current timestamp by more than a threshold programmed
1160 * This field is still valid for MPDU frames without A-MSDU.
1170 * Depending upon mode bit, this field either indicates the
1180 * Depending upon mode bit, this field either indicates the
1189 * Indicates the MSDU number within a MPDU. This value is
1212 * Indicates that either the IP More frag bit is set or IP frag
1213 * number is non-zero. If set indicates that this is a fragmented
1217 * Set if only the TCP Ack bit is set in the TCP flags and if
1225 * 0 - Toeplitz hash of 2-tuple (IP source address, IP
1227 * 1 - Toeplitz hash of 4-tuple (IP source address,
1230 * 2 - Toeplitz of flow_id
1231 * 3 - Zero is used
1234 * Fixed 20-byte IPv4 header or 40-byte IPv6 header parsed
1243 * Fixed 20-byte TCP (excluding TCP options) or 8-byte UDP
1252 * For IPv4, this is the 8 bit protocol field set). For IPv6 this
1253 * is the 8 bit next_header field.
1257 * 2 bytes of C-VLAN Tag Control Information from WHO_L2_LLC
1260 * 2 bytes of S-VLAN Tag Control Information from WHO_L2_LLC
1293 * Bitmap, with each bit indicating if the related spatial
1298 * 0 - spatial stream not used for this reception
1299 * 1 - spatial stream used for this reception
1305 * are all valid. This bit is in the last 64-bit of the descriptor
1309 * Toeplitz hash of 5-tuple
1311 * destination port, L4 protocol} in case of non-IPSec.
1313 * In case of IPSec - Toeplitz hash of 4-tuple
1332 * IPv4/IPv6 - Either, Toeplitz hash computed over 2-tuple
1334 * hash computed over 4-tuple IPv4 or IPv6 src/dest addresses
1337 * is the one used for hash-based REO routing (see use_flow_id_toeplitz_clfy
1345 * and last_mpdu are set in the MSDU then this is a not an
1346 * A-MPDU frame but a stand alone MPDU. Interior MPDU in an
1347 * A-MPDU shall have both first_mpdu and last_mpdu bits set to
1348 * 0. The PPDU start status will only be valid when this bit
1353 * address 1 bit 0 is set indicating mcast/bcast and the BSSID
1366 * Power management bit set in the 802.11 header. Only set
1370 * Set if packet is not a non-QoS data frame. Only set when
1378 * Set if packet is a management packet. Only set when
1382 * Set if packet is a control packet. Only set when first_msdu
1386 * Set if more bit in frame control is set. Only set when
1390 * Set if the EOSP (end of service period) bit in the QoS
1394 * Set if number of MSDUs in A-MSDU is above a threshold or if the
1399 * Set if the order bit in the frame control is set. Only
1435 * Indicates that an A-MSDU with 'from DS = 0' had an SA mismatching
1436 * TA or an A-MDU with 'to DS = 0' had a DA mismatching RA
1448 * MPDU is a directed packet which means that the RA matched
1451 * 'no_ack' bit is the address search entry cleared.
1459 * Indicates that the MPDU was pre-maturely terminated
1460 * resulting in a truncated MPDU. Don't trust the MPDU length
1491 * valid. This bit must be in the last octet of the