Lines Matching +full:host2rxdma +full:- +full:monitor +full:- +full:ring1
1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
13 "mhi-er0",
14 "mhi-er1",
27 "host2wbm-desc-feed",
28 "host2reo-re-injection",
29 "host2reo-command",
30 "host2rxdma-monitor-ring3",
31 "host2rxdma-monitor-ring2",
32 "host2rxdma-monitor-ring1",
33 "reo2ost-exception",
34 "wbm2host-rx-release",
35 "reo2host-status",
36 "reo2host-destination-ring4",
37 "reo2host-destination-ring3",
38 "reo2host-destination-ring2",
39 "reo2host-destination-ring1",
40 "rxdma2host-monitor-destination-mac3",
41 "rxdma2host-monitor-destination-mac2",
42 "rxdma2host-monitor-destination-mac1",
43 "ppdu-end-interrupts-mac3",
44 "ppdu-end-interrupts-mac2",
45 "ppdu-end-interrupts-mac1",
46 "rxdma2host-monitor-status-ring-mac3",
47 "rxdma2host-monitor-status-ring-mac2",
48 "rxdma2host-monitor-status-ring-mac1",
49 "host2rxdma-host-buf-ring-mac3",
50 "host2rxdma-host-buf-ring-mac2",
51 "host2rxdma-host-buf-ring-mac1",
52 "rxdma2host-destination-ring-mac3",
53 "rxdma2host-destination-ring-mac2",
54 "rxdma2host-destination-ring-mac1",
55 "host2tcl-input-ring4",
56 "host2tcl-input-ring3",
57 "host2tcl-input-ring2",
58 "host2tcl-input-ring1",
59 "wbm2host-tx-completions-ring3",
60 "wbm2host-tx-completions-ring2",
61 "wbm2host-tx-completions-ring1",
62 "tcl2host-status-ring",
150 if (msi_config->hw_rev == ab->hw_rev) in ath11k_pcic_init_msi_config()
156 ab->hw_rev); in ath11k_pcic_init_msi_config()
157 return -EINVAL; in ath11k_pcic_init_msi_config()
160 ab->pci.msi.config = msi_config; in ath11k_pcic_init_msi_config()
168 iowrite32(value, ab->mem + offset); in __ath11k_pcic_write32()
170 ab->pci.ops->window_write32(ab, offset, value); in __ath11k_pcic_write32()
178 /* for offset beyond BAR + 4K - 32, may in ath11k_pcic_write32()
181 wakeup_required = test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) && in ath11k_pcic_write32()
183 if (wakeup_required && ab->pci.ops->wakeup) in ath11k_pcic_write32()
184 ret = ab->pci.ops->wakeup(ab); in ath11k_pcic_write32()
188 if (wakeup_required && !ret && ab->pci.ops->release) in ath11k_pcic_write32()
189 ab->pci.ops->release(ab); in ath11k_pcic_write32()
198 val = ioread32(ab->mem + offset); in __ath11k_pcic_read32()
200 val = ab->pci.ops->window_read32(ab, offset); in __ath11k_pcic_read32()
211 /* for offset beyond BAR + 4K - 32, may in ath11k_pcic_read32()
214 wakeup_required = test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) && in ath11k_pcic_read32()
216 if (wakeup_required && ab->pci.ops->wakeup) in ath11k_pcic_read32()
217 ret = ab->pci.ops->wakeup(ab); in ath11k_pcic_read32()
221 if (wakeup_required && !ret && ab->pci.ops->release) in ath11k_pcic_read32()
222 ab->pci.ops->release(ab); in ath11k_pcic_read32()
235 /* for offset beyond BAR + 4K - 32, may in ath11k_pcic_read()
238 wakeup_required = test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) && in ath11k_pcic_read()
240 if (wakeup_required && ab->pci.ops->wakeup) { in ath11k_pcic_read()
241 ret = ab->pci.ops->wakeup(ab); in ath11k_pcic_read()
259 if (wakeup_required && ab->pci.ops->release) in ath11k_pcic_read()
260 ab->pci.ops->release(ab); in ath11k_pcic_read()
269 *msi_addr_lo = ab->pci.msi.addr_lo; in ath11k_pcic_get_msi_address()
270 *msi_addr_hi = ab->pci.msi.addr_hi; in ath11k_pcic_get_msi_address()
278 const struct ath11k_msi_config *msi_config = ab->pci.msi.config; in ath11k_pcic_get_user_msi_assignment()
281 for (idx = 0; idx < msi_config->total_users; idx++) { in ath11k_pcic_get_user_msi_assignment()
282 if (strcmp(user_name, msi_config->users[idx].name) == 0) { in ath11k_pcic_get_user_msi_assignment()
283 *num_vectors = msi_config->users[idx].num_vectors; in ath11k_pcic_get_user_msi_assignment()
284 *base_vector = msi_config->users[idx].base_vector; in ath11k_pcic_get_user_msi_assignment()
285 *user_base_data = *base_vector + ab->pci.msi.ep_base_data; in ath11k_pcic_get_user_msi_assignment()
298 return -EINVAL; in ath11k_pcic_get_user_msi_assignment()
306 for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) { in ath11k_pcic_get_ce_msi_idx()
324 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; in ath11k_pcic_free_ext_irq()
326 for (j = 0; j < irq_grp->num_irq; j++) in ath11k_pcic_free_ext_irq()
327 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp); in ath11k_pcic_free_ext_irq()
329 netif_napi_del(&irq_grp->napi); in ath11k_pcic_free_ext_irq()
330 free_netdev(irq_grp->napi_ndev); in ath11k_pcic_free_ext_irq()
338 for (i = 0; i < ab->hw_params.ce_count; i++) { in ath11k_pcic_free_irq()
342 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]); in ath11k_pcic_free_irq()
356 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags)) in ath11k_pcic_ce_irq_enable()
360 enable_irq(ab->irq_num[irq_idx]); in ath11k_pcic_ce_irq_enable()
370 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags)) in ath11k_pcic_ce_irq_disable()
374 disable_irq_nosync(ab->irq_num[irq_idx]); in ath11k_pcic_ce_irq_disable()
381 clear_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags); in ath11k_pcic_ce_irqs_disable()
383 for (i = 0; i < ab->hw_params.ce_count; i++) { in ath11k_pcic_ce_irqs_disable()
395 for (i = 0; i < ab->hw_params.ce_count; i++) { in ath11k_pcic_sync_ce_irqs()
400 synchronize_irq(ab->irq_num[irq_idx]); in ath11k_pcic_sync_ce_irqs()
407 int irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num; in ath11k_pcic_ce_tasklet()
409 ath11k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num); in ath11k_pcic_ce_tasklet()
411 enable_irq(ce_pipe->ab->irq_num[irq_idx]); in ath11k_pcic_ce_tasklet()
417 struct ath11k_base *ab = ce_pipe->ab; in ath11k_pcic_ce_interrupt_handler()
418 int irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num; in ath11k_pcic_ce_interrupt_handler()
420 if (!test_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags)) in ath11k_pcic_ce_interrupt_handler()
424 ce_pipe->timestamp = jiffies; in ath11k_pcic_ce_interrupt_handler()
426 disable_irq_nosync(ab->irq_num[irq_idx]); in ath11k_pcic_ce_interrupt_handler()
428 tasklet_schedule(&ce_pipe->intr_tq); in ath11k_pcic_ce_interrupt_handler()
435 struct ath11k_base *ab = irq_grp->ab; in ath11k_pcic_ext_grp_disable()
441 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags)) in ath11k_pcic_ext_grp_disable()
444 for (i = 0; i < irq_grp->num_irq; i++) in ath11k_pcic_ext_grp_disable()
445 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); in ath11k_pcic_ext_grp_disable()
452 clear_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags); in __ath11k_pcic_ext_irq_disable()
455 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; in __ath11k_pcic_ext_irq_disable()
459 if (irq_grp->napi_enabled) { in __ath11k_pcic_ext_irq_disable()
460 napi_synchronize(&irq_grp->napi); in __ath11k_pcic_ext_irq_disable()
461 napi_disable(&irq_grp->napi); in __ath11k_pcic_ext_irq_disable()
462 irq_grp->napi_enabled = false; in __ath11k_pcic_ext_irq_disable()
469 struct ath11k_base *ab = irq_grp->ab; in ath11k_pcic_ext_grp_enable()
475 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags)) in ath11k_pcic_ext_grp_enable()
478 for (i = 0; i < irq_grp->num_irq; i++) in ath11k_pcic_ext_grp_enable()
479 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); in ath11k_pcic_ext_grp_enable()
487 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; in ath11k_pcic_ext_irq_enable()
489 if (!irq_grp->napi_enabled) { in ath11k_pcic_ext_irq_enable()
490 napi_enable(&irq_grp->napi); in ath11k_pcic_ext_irq_enable()
491 irq_grp->napi_enabled = true; in ath11k_pcic_ext_irq_enable()
496 set_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags); in ath11k_pcic_ext_irq_enable()
505 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; in ath11k_pcic_sync_ext_irqs()
507 for (j = 0; j < irq_grp->num_irq; j++) { in ath11k_pcic_sync_ext_irqs()
508 irq_idx = irq_grp->irqs[j]; in ath11k_pcic_sync_ext_irqs()
509 synchronize_irq(ab->irq_num[irq_idx]); in ath11k_pcic_sync_ext_irqs()
526 struct ath11k_base *ab = irq_grp->ab; in ath11k_pcic_ext_grp_napi_poll()
533 for (i = 0; i < irq_grp->num_irq; i++) in ath11k_pcic_ext_grp_napi_poll()
534 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); in ath11k_pcic_ext_grp_napi_poll()
546 struct ath11k_base *ab = irq_grp->ab; in ath11k_pcic_ext_interrupt_handler()
549 if (!test_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags)) in ath11k_pcic_ext_interrupt_handler()
552 ath11k_dbg(irq_grp->ab, ATH11K_DBG_PCI, "ext irq %d\n", irq); in ath11k_pcic_ext_interrupt_handler()
555 irq_grp->timestamp = jiffies; in ath11k_pcic_ext_interrupt_handler()
557 for (i = 0; i < irq_grp->num_irq; i++) in ath11k_pcic_ext_interrupt_handler()
558 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); in ath11k_pcic_ext_interrupt_handler()
560 napi_schedule(&irq_grp->napi); in ath11k_pcic_ext_interrupt_handler()
568 return ab->pci.ops->get_msi_irq(ab, vector); in ath11k_pcic_get_msi_irq()
585 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags)) in ath11k_pcic_ext_irq_config()
589 irq_grp = &ab->ext_irq_grp[i]; in ath11k_pcic_ext_irq_config()
592 irq_grp->ab = ab; in ath11k_pcic_ext_irq_config()
593 irq_grp->grp_id = i; in ath11k_pcic_ext_irq_config()
594 irq_grp->napi_ndev = alloc_netdev_dummy(0); in ath11k_pcic_ext_irq_config()
595 if (!irq_grp->napi_ndev) { in ath11k_pcic_ext_irq_config()
596 ret = -ENOMEM; in ath11k_pcic_ext_irq_config()
600 netif_napi_add(irq_grp->napi_ndev, &irq_grp->napi, in ath11k_pcic_ext_irq_config()
603 if (ab->hw_params.ring_mask->tx[i] || in ath11k_pcic_ext_irq_config()
604 ab->hw_params.ring_mask->rx[i] || in ath11k_pcic_ext_irq_config()
605 ab->hw_params.ring_mask->rx_err[i] || in ath11k_pcic_ext_irq_config()
606 ab->hw_params.ring_mask->rx_wbm_rel[i] || in ath11k_pcic_ext_irq_config()
607 ab->hw_params.ring_mask->reo_status[i] || in ath11k_pcic_ext_irq_config()
608 ab->hw_params.ring_mask->rxdma2host[i] || in ath11k_pcic_ext_irq_config()
609 ab->hw_params.ring_mask->host2rxdma[i] || in ath11k_pcic_ext_irq_config()
610 ab->hw_params.ring_mask->rx_mon_status[i]) { in ath11k_pcic_ext_irq_config()
614 irq_grp->num_irq = num_irq; in ath11k_pcic_ext_irq_config()
615 irq_grp->irqs[0] = ATH11K_PCI_IRQ_DP_OFFSET + i; in ath11k_pcic_ext_irq_config()
617 for (j = 0; j < irq_grp->num_irq; j++) { in ath11k_pcic_ext_irq_config()
618 int irq_idx = irq_grp->irqs[j]; in ath11k_pcic_ext_irq_config()
627 ab->irq_num[irq_idx] = irq; in ath11k_pcic_ext_irq_config()
639 irq_grp = &ab->ext_irq_grp[n]; in ath11k_pcic_ext_irq_config()
640 free_netdev(irq_grp->napi_ndev); in ath11k_pcic_ext_irq_config()
650 /* i ->napi_ndev was properly allocated. Free it also */ in ath11k_pcic_ext_irq_config()
654 irq_grp = &ab->ext_irq_grp[n]; in ath11k_pcic_ext_irq_config()
655 free_netdev(irq_grp->napi_ndev); in ath11k_pcic_ext_irq_config()
676 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags)) in ath11k_pcic_config_irq()
680 for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) { in ath11k_pcic_config_irq()
689 ce_pipe = &ab->ce.ce_pipe[i]; in ath11k_pcic_config_irq()
693 tasklet_setup(&ce_pipe->intr_tq, ath11k_pcic_ce_tasklet); in ath11k_pcic_config_irq()
703 ab->irq_num[irq_idx] = irq; in ath11k_pcic_config_irq()
721 set_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags); in ath11k_pcic_ce_irqs_enable()
723 for (i = 0; i < ab->hw_params.ce_count; i++) { in ath11k_pcic_ce_irqs_enable()
735 for (i = 0; i < ab->hw_params.ce_count; i++) { in ath11k_pcic_kill_tasklets()
736 struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; in ath11k_pcic_kill_tasklets()
741 tasklet_kill(&ce_pipe->intr_tq); in ath11k_pcic_kill_tasklets()
762 set_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags); in ath11k_pcic_start()
778 for (i = 0; i < ab->hw_params.svc_to_ce_map_len; i++) { in ath11k_pcic_map_service_to_pipe()
779 entry = &ab->hw_params.svc_to_ce_map[i]; in ath11k_pcic_map_service_to_pipe()
781 if (__le32_to_cpu(entry->service_id) != service_id) in ath11k_pcic_map_service_to_pipe()
784 switch (__le32_to_cpu(entry->pipedir)) { in ath11k_pcic_map_service_to_pipe()
789 *dl_pipe = __le32_to_cpu(entry->pipenum); in ath11k_pcic_map_service_to_pipe()
794 *ul_pipe = __le32_to_cpu(entry->pipenum); in ath11k_pcic_map_service_to_pipe()
800 *dl_pipe = __le32_to_cpu(entry->pipenum); in ath11k_pcic_map_service_to_pipe()
801 *ul_pipe = __le32_to_cpu(entry->pipenum); in ath11k_pcic_map_service_to_pipe()
809 return -ENOENT; in ath11k_pcic_map_service_to_pipe()
822 if (!pci_ops->get_msi_irq || !pci_ops->window_write32 || in ath11k_pcic_register_pci_ops()
823 !pci_ops->window_read32) in ath11k_pcic_register_pci_ops()
824 return -EINVAL; in ath11k_pcic_register_pci_ops()
826 ab->pci.ops = pci_ops; in ath11k_pcic_register_pci_ops()
835 for (i = 0; i < ab->hw_params.ce_count; i++) { in ath11k_pci_enable_ce_irqs_except_wake_irq()
850 for (i = 0; i < ab->hw_params.ce_count; i++) { in ath11k_pci_disable_ce_irqs_except_wake_irq()
851 ce_pipe = &ab->ce.ce_pipe[i]; in ath11k_pci_disable_ce_irqs_except_wake_irq()
858 disable_irq_nosync(ab->irq_num[irq_idx]); in ath11k_pci_disable_ce_irqs_except_wake_irq()
859 synchronize_irq(ab->irq_num[irq_idx]); in ath11k_pci_disable_ce_irqs_except_wake_irq()
860 tasklet_kill(&ce_pipe->intr_tq); in ath11k_pci_disable_ce_irqs_except_wake_irq()