21 	case 0:  in ath11k_hw_ipq8074_mac_from_pdev_id()
22 		return 0;  in ath11k_hw_ipq8074_mac_from_pdev_id()
71 	config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;  in ath11k_init_wmi_config_qca6390()
80 	config->num_mcast_groups = 0;  in ath11k_init_wmi_config_qca6390()
81 	config->num_mcast_table_elems = 0;  in ath11k_init_wmi_config_qca6390()
82 	config->mcast2ucast_mode = 0;  in ath11k_init_wmi_config_qca6390()
84 	config->num_wds_entries = 0;  in ath11k_init_wmi_config_qca6390()
85 	config->dma_burst_size = 0;  in ath11k_init_wmi_config_qca6390()
86 	config->rx_skip_defrag_timeout_dup_detection_check = 0;  in ath11k_init_wmi_config_qca6390()
89 	config->num_msdu_desc = 0x400;  in ath11k_init_wmi_config_qca6390()
93 	config->peer_map_unmap_v2_support = 0;  in ath11k_init_wmi_config_qca6390()
95 	config->max_frag_entries = 0xa;  in ath11k_init_wmi_config_qca6390()
96 	config->num_tdls_vdevs = 0x1;  in ath11k_init_wmi_config_qca6390()
98 	config->beacon_tx_offload_max_vdev = 0x2;  in ath11k_init_wmi_config_qca6390()
99 	config->num_multicast_filter_entries = 0x20;  in ath11k_init_wmi_config_qca6390()
100 	config->num_wow_filters = 0x16;  in ath11k_init_wmi_config_qca6390()
101 	config->num_keep_alive_pattern = 0;  in ath11k_init_wmi_config_qca6390()
110 	u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |  in ath11k_hw_ipq8074_reo_setup()
173 	config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;  in ath11k_init_wmi_config_ipq8074()
219 	return 0;  in ath11k_hw_mac_id_to_srng_id_ipq8074()
225 	return 0;  in ath11k_hw_mac_id_to_pdev_id_qca6390()
408 	return &desc->u.ipq8074.msdu_payload[0];  in ath11k_hw_ipq8074_rx_desc_get_msdu_payload()
574 	return &desc->u.qcn9074.msdu_payload[0];  in ath11k_hw_qcn9074_rx_desc_get_msdu_payload()
745 	return &desc->u.wcn6855.msdu_payload[0];  in ath11k_hw_wcn6855_rx_desc_get_msdu_payload()
764 	u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |  in ath11k_hw_wcn6855_reo_setup()
804 	u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |  in ath11k_hw_ipq5018_reo_setup()
844 	u16 peer_id = 0;  in ath11k_hw_ipq8074_mpdu_info_get_peerid()
855 	u16 peer_id = 0;  in ath11k_hw_qcn9074_mpdu_info_get_peerid()
866 	u16 peer_id = 0;  in ath11k_hw_wcn6855_mpdu_info_get_peerid()
1184 #define ATH11K_TX_RING_MASK_0 BIT(0)
1190 #define ATH11K_RX_RING_MASK_0 0x1
1191 #define ATH11K_RX_RING_MASK_1 0x2
1192 #define ATH11K_RX_RING_MASK_2 0x4
1193 #define ATH11K_RX_RING_MASK_3 0x8
1195 #define ATH11K_RX_ERR_RING_MASK_0 0x1
1197 #define ATH11K_RX_WBM_REL_RING_MASK_0 0x1
1199 #define ATH11K_REO_STATUS_RING_MASK_0 0x1
1201 #define ATH11K_RXDMA2HOST_RING_MASK_0 0x1
1202 #define ATH11K_RXDMA2HOST_RING_MASK_1 0x2
1203 #define ATH11K_RXDMA2HOST_RING_MASK_2 0x4
1205 #define ATH11K_HOST2RXDMA_RING_MASK_0 0x1
1206 #define ATH11K_HOST2RXDMA_RING_MASK_1 0x2
1207 #define ATH11K_HOST2RXDMA_RING_MASK_2 0x4
1209 #define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1
1210 #define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2
1211 #define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4
1220 		0, 0, 0, 0,
1226 		0, 0, 0, 0, 0, 0, 0,
1239 		0, 0, 0,
1259 		0, 0, 0, 0,
1265 		0, 0, 0, 0, 0, 0, 0,
1293 		.pipenum = __cpu_to_le32(0),
1298 		.reserved = __cpu_to_le32(0),
1308 		.reserved = __cpu_to_le32(0),
1318 		.reserved = __cpu_to_le32(0),
1328 		.reserved = __cpu_to_le32(0),
1338 		.reserved = __cpu_to_le32(0),
1347 		.flags = __cpu_to_le32(0),
1348 		.reserved = __cpu_to_le32(0),
1358 		.reserved = __cpu_to_le32(0),
1368 		.reserved = __cpu_to_le32(0),
1378 		.reserved = __cpu_to_le32(0),
1388 		.reserved = __cpu_to_le32(0),
1395 		.nentries = __cpu_to_le32(0),
1396 		.nbytes_max = __cpu_to_le32(0),
1398 		.reserved = __cpu_to_le32(0),
1482 		.pipenum = __cpu_to_le32(0),
1492 		.pipenum = __cpu_to_le32(0),
1584 		.pipenum = __cpu_to_le32(0),
1594 		.pipenum = __cpu_to_le32(0),
1626 		.pipenum = __cpu_to_le32(0),
1631 		.reserved = __cpu_to_le32(0),
1641 		.reserved = __cpu_to_le32(0),
1651 		.reserved = __cpu_to_le32(0),
1661 		.reserved = __cpu_to_le32(0),
1671 		.reserved = __cpu_to_le32(0),
1681 		.reserved = __cpu_to_le32(0),
1691 		.reserved = __cpu_to_le32(0),
1698 		.nentries = __cpu_to_le32(0),
1699 		.nbytes_max = __cpu_to_le32(0),
1701 		.reserved = __cpu_to_le32(0),
1711 		.reserved = __cpu_to_le32(0),
1774 		__cpu_to_le32(0),
1795 		__cpu_to_le32(0),
1796 		__cpu_to_le32(0),
1797 		__cpu_to_le32(0),
1805 		.pipenum = __cpu_to_le32(0),
1810 		.reserved = __cpu_to_le32(0),
1820 		.reserved = __cpu_to_le32(0),
1830 		.reserved = __cpu_to_le32(0),
1840 		.reserved = __cpu_to_le32(0),
1850 		.reserved = __cpu_to_le32(0),
1860 		.reserved = __cpu_to_le32(0),
1870 		.reserved = __cpu_to_le32(0),
1877 		.nentries = __cpu_to_le32(0),
1878 		.nbytes_max = __cpu_to_le32(0),
1880 		.reserved = __cpu_to_le32(0),
1890 		.reserved = __cpu_to_le32(0),
1953 		__cpu_to_le32(0),
1963 		__cpu_to_le32(0),
1989 		__cpu_to_le32(0),
1990 		__cpu_to_le32(0),
1991 		__cpu_to_le32(0),
2002 		0, 0, 0,
2008 		0, 0, 0, 0,
2015 		0, 0, 0,
2019 		0, 0, 0,
2023 		0, 0, 0,
2027 		0, 0, 0,
2031 		0, 0, 0,
2039 		0,
2041 		0,
2045 		0, 0, 0, 0, 0, 0,
2049 		0, 0, 0, 0, 0, 0, 0,
2056 		0, ATH11K_RX_ERR_RING_MASK_0,
2059 		0, ATH11K_RX_WBM_REL_RING_MASK_0,
2062 		0, ATH11K_REO_STATUS_RING_MASK_0,
2077 		.pipenum = __cpu_to_le32(0),
2082 		.reserved = __cpu_to_le32(0),
2092 		.reserved = __cpu_to_le32(0),
2102 		.reserved = __cpu_to_le32(0),
2112 		.reserved = __cpu_to_le32(0),
2122 		.reserved = __cpu_to_le32(0),
2132 		.reserved = __cpu_to_le32(0),
2142 		.reserved = __cpu_to_le32(0),
2151 		.flags = __cpu_to_le32(0x2000),
2152 		.reserved = __cpu_to_le32(0),
2162 		.reserved = __cpu_to_le32(0),
2225 		.pipenum = __cpu_to_le32(0),
2236 		.pipenum = __cpu_to_le32(0),
2283 	.hal_tcl1_ring_base_lsb = 0x00000510,
2284 	.hal_tcl1_ring_base_msb = 0x00000514,
2285 	.hal_tcl1_ring_id = 0x00000518,
2286 	.hal_tcl1_ring_misc = 0x00000520,
2287 	.hal_tcl1_ring_tp_addr_lsb = 0x0000052c,
2288 	.hal_tcl1_ring_tp_addr_msb = 0x00000530,
2289 	.hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540,
2290 	.hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544,
2291 	.hal_tcl1_ring_msi1_base_lsb = 0x00000558,
2292 	.hal_tcl1_ring_msi1_base_msb = 0x0000055c,
2293 	.hal_tcl1_ring_msi1_data = 0x00000560,
2294 	.hal_tcl2_ring_base_lsb = 0x00000568,
2295 	.hal_tcl_ring_base_lsb = 0x00000618,
2298 	.hal_tcl_status_ring_base_lsb = 0x00000720,
2301 	.hal_reo1_ring_base_lsb = 0x0000029c,
2302 	.hal_reo1_ring_base_msb = 0x000002a0,
2303 	.hal_reo1_ring_id = 0x000002a4,
2304 	.hal_reo1_ring_misc = 0x000002ac,
2305 	.hal_reo1_ring_hp_addr_lsb = 0x000002b0,
2306 	.hal_reo1_ring_hp_addr_msb = 0x000002b4,
2307 	.hal_reo1_ring_producer_int_setup = 0x000002c0,
2308 	.hal_reo1_ring_msi1_base_lsb = 0x000002e4,
2309 	.hal_reo1_ring_msi1_base_msb = 0x000002e8,
2310 	.hal_reo1_ring_msi1_data = 0x000002ec,
2311 	.hal_reo2_ring_base_lsb = 0x000002f4,
2312 	.hal_reo1_aging_thresh_ix_0 = 0x00000564,
2313 	.hal_reo1_aging_thresh_ix_1 = 0x00000568,
2314 	.hal_reo1_aging_thresh_ix_2 = 0x0000056c,
2315 	.hal_reo1_aging_thresh_ix_3 = 0x00000570,
2318 	.hal_reo1_ring_hp = 0x00003038,
2319 	.hal_reo1_ring_tp = 0x0000303c,
2320 	.hal_reo2_ring_hp = 0x00003040,
2323 	.hal_reo_tcl_ring_base_lsb = 0x000003fc,
2324 	.hal_reo_tcl_ring_hp = 0x00003058,
2327 	.hal_reo_cmd_ring_base_lsb = 0x00000194,
2328 	.hal_reo_cmd_ring_hp = 0x00003020,
2331 	.hal_reo_status_ring_base_lsb = 0x00000504,
2332 	.hal_reo_status_hp = 0x00003070,
2335 	.hal_sw2reo_ring_base_lsb = 0x000001ec,
2336 	.hal_sw2reo_ring_hp = 0x00003028,
2339 	.hal_seq_wcss_umac_ce0_src_reg = 0x00a00000,
2340 	.hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000,
2341 	.hal_seq_wcss_umac_ce1_src_reg = 0x00a02000,
2342 	.hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000,
2345 	.hal_wbm_idle_link_ring_base_lsb = 0x00000860,
2346 	.hal_wbm_idle_link_ring_misc = 0x00000870,
2349 	.hal_wbm_release_ring_base_lsb = 0x000001d8,
2352 	.hal_wbm0_release_ring_base_lsb = 0x00000910,
2353 	.hal_wbm1_release_ring_base_lsb = 0x00000968,
2356 	.pcie_qserdes_sysclk_en_sel = 0x0,
2357 	.pcie_pcs_osc_dtct_config_base = 0x0,
2360 	.hal_shadow_base_addr = 0x0,
2363 	.hal_reo1_misc_ctl = 0x0,
2368 	.hal_tcl1_ring_base_lsb = 0x00000684,
2369 	.hal_tcl1_ring_base_msb = 0x00000688,
2370 	.hal_tcl1_ring_id = 0x0000068c,
2371 	.hal_tcl1_ring_misc = 0x00000694,
2372 	.hal_tcl1_ring_tp_addr_lsb = 0x000006a0,
2373 	.hal_tcl1_ring_tp_addr_msb = 0x000006a4,
2374 	.hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4,
2375 	.hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8,
2376 	.hal_tcl1_ring_msi1_base_lsb = 0x000006cc,
2377 	.hal_tcl1_ring_msi1_base_msb = 0x000006d0,
2378 	.hal_tcl1_ring_msi1_data = 0x000006d4,
2379 	.hal_tcl2_ring_base_lsb = 0x000006dc,
2380 	.hal_tcl_ring_base_lsb = 0x0000078c,
2383 	.hal_tcl_status_ring_base_lsb = 0x00000894,
2386 	.hal_reo1_ring_base_lsb = 0x00000244,
2387 	.hal_reo1_ring_base_msb = 0x00000248,
2388 	.hal_reo1_ring_id = 0x0000024c,
2389 	.hal_reo1_ring_misc = 0x00000254,
2390 	.hal_reo1_ring_hp_addr_lsb = 0x00000258,
2391 	.hal_reo1_ring_hp_addr_msb = 0x0000025c,
2392 	.hal_reo1_ring_producer_int_setup = 0x00000268,
2393 	.hal_reo1_ring_msi1_base_lsb = 0x0000028c,
2394 	.hal_reo1_ring_msi1_base_msb = 0x00000290,
2395 	.hal_reo1_ring_msi1_data = 0x00000294,
2396 	.hal_reo2_ring_base_lsb = 0x0000029c,
2397 	.hal_reo1_aging_thresh_ix_0 = 0x0000050c,
2398 	.hal_reo1_aging_thresh_ix_1 = 0x00000510,
2399 	.hal_reo1_aging_thresh_ix_2 = 0x00000514,
2400 	.hal_reo1_aging_thresh_ix_3 = 0x00000518,
2403 	.hal_reo1_ring_hp = 0x00003030,
2404 	.hal_reo1_ring_tp = 0x00003034,
2405 	.hal_reo2_ring_hp = 0x00003038,
2408 	.hal_reo_tcl_ring_base_lsb = 0x000003a4,
2409 	.hal_reo_tcl_ring_hp = 0x00003050,
2412 	.hal_reo_cmd_ring_base_lsb = 0x00000194,
2413 	.hal_reo_cmd_ring_hp = 0x00003020,
2416 	.hal_reo_status_ring_base_lsb = 0x000004ac,
2417 	.hal_reo_status_hp = 0x00003068,
2420 	.hal_sw2reo_ring_base_lsb = 0x000001ec,
2421 	.hal_sw2reo_ring_hp = 0x00003028,
2424 	.hal_seq_wcss_umac_ce0_src_reg = 0x00a00000,
2425 	.hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000,
2426 	.hal_seq_wcss_umac_ce1_src_reg = 0x00a02000,
2427 	.hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000,
2430 	.hal_wbm_idle_link_ring_base_lsb = 0x00000860,
2431 	.hal_wbm_idle_link_ring_misc = 0x00000870,
2434 	.hal_wbm_release_ring_base_lsb = 0x000001d8,
2437 	.hal_wbm0_release_ring_base_lsb = 0x00000910,
2438 	.hal_wbm1_release_ring_base_lsb = 0x00000968,
2441 	.pcie_qserdes_sysclk_en_sel = 0x01e0c0ac,
2442 	.pcie_pcs_osc_dtct_config_base = 0x01e0c628,
2445 	.hal_shadow_base_addr = 0x000008fc,
2448 	.hal_reo1_misc_ctl = 0x0,
2453 	.hal_tcl1_ring_base_lsb = 0x000004f0,
2454 	.hal_tcl1_ring_base_msb = 0x000004f4,
2455 	.hal_tcl1_ring_id = 0x000004f8,
2456 	.hal_tcl1_ring_misc = 0x00000500,
2457 	.hal_tcl1_ring_tp_addr_lsb = 0x0000050c,
2458 	.hal_tcl1_ring_tp_addr_msb = 0x00000510,
2459 	.hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000520,
2460 	.hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000524,
2461 	.hal_tcl1_ring_msi1_base_lsb = 0x00000538,
2462 	.hal_tcl1_ring_msi1_base_msb = 0x0000053c,
2463 	.hal_tcl1_ring_msi1_data = 0x00000540,
2464 	.hal_tcl2_ring_base_lsb = 0x00000548,
2465 	.hal_tcl_ring_base_lsb = 0x000005f8,
2468 	.hal_tcl_status_ring_base_lsb = 0x00000700,
2471 	.hal_reo1_ring_base_lsb = 0x0000029c,
2472 	.hal_reo1_ring_base_msb = 0x000002a0,
2473 	.hal_reo1_ring_id = 0x000002a4,
2474 	.hal_reo1_ring_misc = 0x000002ac,
2475 	.hal_reo1_ring_hp_addr_lsb = 0x000002b0,
2476 	.hal_reo1_ring_hp_addr_msb = 0x000002b4,
2477 	.hal_reo1_ring_producer_int_setup = 0x000002c0,
2478 	.hal_reo1_ring_msi1_base_lsb = 0x000002e4,
2479 	.hal_reo1_ring_msi1_base_msb = 0x000002e8,
2480 	.hal_reo1_ring_msi1_data = 0x000002ec,
2481 	.hal_reo2_ring_base_lsb = 0x000002f4,
2482 	.hal_reo1_aging_thresh_ix_0 = 0x00000564,
2483 	.hal_reo1_aging_thresh_ix_1 = 0x00000568,
2484 	.hal_reo1_aging_thresh_ix_2 = 0x0000056c,
2485 	.hal_reo1_aging_thresh_ix_3 = 0x00000570,
2488 	.hal_reo1_ring_hp = 0x00003038,
2489 	.hal_reo1_ring_tp = 0x0000303c,
2490 	.hal_reo2_ring_hp = 0x00003040,
2493 	.hal_reo_tcl_ring_base_lsb = 0x000003fc,
2494 	.hal_reo_tcl_ring_hp = 0x00003058,
2497 	.hal_reo_cmd_ring_base_lsb = 0x00000194,
2498 	.hal_reo_cmd_ring_hp = 0x00003020,
2501 	.hal_reo_status_ring_base_lsb = 0x00000504,
2502 	.hal_reo_status_hp = 0x00003070,
2505 	.hal_sw2reo_ring_base_lsb = 0x000001ec,
2506 	.hal_sw2reo_ring_hp = 0x00003028,
2509 	.hal_seq_wcss_umac_ce0_src_reg = 0x01b80000,
2510 	.hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000,
2511 	.hal_seq_wcss_umac_ce1_src_reg = 0x01b82000,
2512 	.hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000,
2515 	.hal_wbm_idle_link_ring_base_lsb = 0x00000874,
2516 	.hal_wbm_idle_link_ring_misc = 0x00000884,
2519 	.hal_wbm_release_ring_base_lsb = 0x000001ec,
2522 	.hal_wbm0_release_ring_base_lsb = 0x00000924,
2523 	.hal_wbm1_release_ring_base_lsb = 0x0000097c,
2526 	.pcie_qserdes_sysclk_en_sel = 0x01e0e0a8,
2527 	.pcie_pcs_osc_dtct_config_base = 0x01e0f45c,
2530 	.hal_shadow_base_addr = 0x0,
2533 	.hal_reo1_misc_ctl = 0x0,
2538 	.hal_tcl1_ring_base_lsb = 0x00000690,
2539 	.hal_tcl1_ring_base_msb = 0x00000694,
2540 	.hal_tcl1_ring_id = 0x00000698,
2541 	.hal_tcl1_ring_misc = 0x000006a0,
2542 	.hal_tcl1_ring_tp_addr_lsb = 0x000006ac,
2543 	.hal_tcl1_ring_tp_addr_msb = 0x000006b0,
2544 	.hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c0,
2545 	.hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c4,
2546 	.hal_tcl1_ring_msi1_base_lsb = 0x000006d8,
2547 	.hal_tcl1_ring_msi1_base_msb = 0x000006dc,
2548 	.hal_tcl1_ring_msi1_data = 0x000006e0,
2549 	.hal_tcl2_ring_base_lsb = 0x000006e8,
2550 	.hal_tcl_ring_base_lsb = 0x00000798,
2553 	.hal_tcl_status_ring_base_lsb = 0x000008a0,
2556 	.hal_reo1_ring_base_lsb = 0x00000244,
2557 	.hal_reo1_ring_base_msb = 0x00000248,
2558 	.hal_reo1_ring_id = 0x0000024c,
2559 	.hal_reo1_ring_misc = 0x00000254,
2560 	.hal_reo1_ring_hp_addr_lsb = 0x00000258,
2561 	.hal_reo1_ring_hp_addr_msb = 0x0000025c,
2562 	.hal_reo1_ring_producer_int_setup = 0x00000268,
2563 	.hal_reo1_ring_msi1_base_lsb = 0x0000028c,
2564 	.hal_reo1_ring_msi1_base_msb = 0x00000290,
2565 	.hal_reo1_ring_msi1_data = 0x00000294,
2566 	.hal_reo2_ring_base_lsb = 0x0000029c,
2567 	.hal_reo1_aging_thresh_ix_0 = 0x000005bc,
2568 	.hal_reo1_aging_thresh_ix_1 = 0x000005c0,
2569 	.hal_reo1_aging_thresh_ix_2 = 0x000005c4,
2570 	.hal_reo1_aging_thresh_ix_3 = 0x000005c8,
2573 	.hal_reo1_ring_hp = 0x00003030,
2574 	.hal_reo1_ring_tp = 0x00003034,
2575 	.hal_reo2_ring_hp = 0x00003038,
2578 	.hal_reo_tcl_ring_base_lsb = 0x00000454,
2579 	.hal_reo_tcl_ring_hp = 0x00003060,
2582 	.hal_reo_cmd_ring_base_lsb = 0x00000194,
2583 	.hal_reo_cmd_ring_hp = 0x00003020,
2586 	.hal_reo_status_ring_base_lsb = 0x0000055c,
2587 	.hal_reo_status_hp = 0x00003078,
2590 	.hal_sw2reo_ring_base_lsb = 0x000001ec,
2591 	.hal_sw2reo_ring_hp = 0x00003028,
2594 	.hal_seq_wcss_umac_ce0_src_reg = 0x1b80000,
2595 	.hal_seq_wcss_umac_ce0_dst_reg = 0x1b81000,
2596 	.hal_seq_wcss_umac_ce1_src_reg = 0x1b82000,
2597 	.hal_seq_wcss_umac_ce1_dst_reg = 0x1b83000,
2600 	.hal_wbm_idle_link_ring_base_lsb = 0x00000870,
2601 	.hal_wbm_idle_link_ring_misc = 0x00000880,
2604 	.hal_wbm_release_ring_base_lsb = 0x000001e8,
2607 	.hal_wbm0_release_ring_base_lsb = 0x00000920,
2608 	.hal_wbm1_release_ring_base_lsb = 0x00000978,
2611 	.pcie_qserdes_sysclk_en_sel = 0x01e0c0ac,
2612 	.pcie_pcs_osc_dtct_config_base = 0x01e0c628,
2615 	.hal_shadow_base_addr = 0x000008fc,
2620 	.hal_reo1_misc_ctl = 0x00000630,
2625 	.hal_tcl1_ring_base_lsb = 0x00000694,
2626 	.hal_tcl1_ring_base_msb = 0x00000698,
2627 	.hal_tcl1_ring_id = 0x0000069c,
2628 	.hal_tcl1_ring_misc = 0x000006a4,
2629 	.hal_tcl1_ring_tp_addr_lsb = 0x000006b0,
2630 	.hal_tcl1_ring_tp_addr_msb = 0x000006b4,
2631 	.hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c4,
2632 	.hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c8,
2633 	.hal_tcl1_ring_msi1_base_lsb = 0x000006dc,
2634 	.hal_tcl1_ring_msi1_base_msb = 0x000006e0,
2635 	.hal_tcl1_ring_msi1_data = 0x000006e4,
2636 	.hal_tcl2_ring_base_lsb = 0x000006ec,
2637 	.hal_tcl_ring_base_lsb = 0x0000079c,
2640 	.hal_tcl_status_ring_base_lsb = 0x000008a4,
2643 	.hal_reo1_ring_base_lsb = 0x000001ec,
2644 	.hal_reo1_ring_base_msb = 0x000001f0,
2645 	.hal_reo1_ring_id = 0x000001f4,
2646 	.hal_reo1_ring_misc = 0x000001fc,
2647 	.hal_reo1_ring_hp_addr_lsb = 0x00000200,
2648 	.hal_reo1_ring_hp_addr_msb = 0x00000204,
2649 	.hal_reo1_ring_producer_int_setup = 0x00000210,
2650 	.hal_reo1_ring_msi1_base_lsb = 0x00000234,
2651 	.hal_reo1_ring_msi1_base_msb = 0x00000238,
2652 	.hal_reo1_ring_msi1_data = 0x0000023c,
2653 	.hal_reo2_ring_base_lsb = 0x00000244,
2654 	.hal_reo1_aging_thresh_ix_0 = 0x00000564,
2655 	.hal_reo1_aging_thresh_ix_1 = 0x00000568,
2656 	.hal_reo1_aging_thresh_ix_2 = 0x0000056c,
2657 	.hal_reo1_aging_thresh_ix_3 = 0x00000570,
2660 	.hal_reo1_ring_hp = 0x00003028,
2661 	.hal_reo1_ring_tp = 0x0000302c,
2662 	.hal_reo2_ring_hp = 0x00003030,
2665 	.hal_reo_tcl_ring_base_lsb = 0x000003fc,
2666 	.hal_reo_tcl_ring_hp = 0x00003058,
2669 	.hal_reo_cmd_ring_base_lsb = 0x000000e4,
2670 	.hal_reo_cmd_ring_hp = 0x00003010,
2673 	.hal_reo_status_ring_base_lsb = 0x00000504,
2674 	.hal_reo_status_hp = 0x00003070,
2677 	.hal_sw2reo_ring_base_lsb = 0x0000013c,
2678 	.hal_sw2reo_ring_hp = 0x00003018,
2681 	.hal_seq_wcss_umac_ce0_src_reg = 0x01b80000,
2682 	.hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000,
2683 	.hal_seq_wcss_umac_ce1_src_reg = 0x01b82000,
2684 	.hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000,
2687 	.hal_wbm_idle_link_ring_base_lsb = 0x00000874,
2688 	.hal_wbm_idle_link_ring_misc = 0x00000884,
2691 	.hal_wbm_release_ring_base_lsb = 0x000001ec,
2694 	.hal_wbm0_release_ring_base_lsb = 0x00000924,
2695 	.hal_wbm1_release_ring_base_lsb = 0x0000097c,
2698 	.pcie_qserdes_sysclk_en_sel = 0x0,
2699 	.pcie_pcs_osc_dtct_config_base = 0x0,
2702 	.hal_shadow_base_addr = 0x00000504,
2707 	.hal_reo1_misc_ctl = 0x000005d8,
2712 		.tcl_ring_num = 0,
2713 		.wbm_ring_num = 0,
2730 		.tcl_ring_num = 0,
2731 		.wbm_ring_num = 0,
2748 	.hal_tcl1_ring_base_lsb = 0x00000694,
2749 	.hal_tcl1_ring_base_msb = 0x00000698,
2750 	.hal_tcl1_ring_id =	0x0000069c,
2751 	.hal_tcl1_ring_misc = 0x000006a4,
2752 	.hal_tcl1_ring_tp_addr_lsb = 0x000006b0,
2753 	.hal_tcl1_ring_tp_addr_msb = 0x000006b4,
2754 	.hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c4,
2755 	.hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c8,
2756 	.hal_tcl1_ring_msi1_base_lsb = 0x000006dc,
2757 	.hal_tcl1_ring_msi1_base_msb = 0x000006e0,
2758 	.hal_tcl1_ring_msi1_data = 0x000006e4,
2759 	.hal_tcl2_ring_base_lsb = 0x000006ec,
2760 	.hal_tcl_ring_base_lsb = 0x0000079c,
2763 	.hal_tcl_status_ring_base_lsb = 0x000008a4,
2766 	.hal_reo1_ring_base_lsb = 0x000001ec,
2767 	.hal_reo1_ring_base_msb = 0x000001f0,
2768 	.hal_reo1_ring_id = 0x000001f4,
2769 	.hal_reo1_ring_misc = 0x000001fc,
2770 	.hal_reo1_ring_hp_addr_lsb = 0x00000200,
2771 	.hal_reo1_ring_hp_addr_msb = 0x00000204,
2772 	.hal_reo1_ring_producer_int_setup = 0x00000210,
2773 	.hal_reo1_ring_msi1_base_lsb = 0x00000234,
2774 	.hal_reo1_ring_msi1_base_msb = 0x00000238,
2775 	.hal_reo1_ring_msi1_data = 0x0000023c,
2776 	.hal_reo2_ring_base_lsb = 0x00000244,
2777 	.hal_reo1_aging_thresh_ix_0 = 0x00000564,
2778 	.hal_reo1_aging_thresh_ix_1 = 0x00000568,
2779 	.hal_reo1_aging_thresh_ix_2 = 0x0000056c,
2780 	.hal_reo1_aging_thresh_ix_3 = 0x00000570,
2783 	.hal_reo1_ring_hp = 0x00003028,
2784 	.hal_reo1_ring_tp = 0x0000302c,
2785 	.hal_reo2_ring_hp = 0x00003030,
2788 	.hal_reo_tcl_ring_base_lsb = 0x000003fc,
2789 	.hal_reo_tcl_ring_hp = 0x00003058,
2792 	.hal_sw2reo_ring_base_lsb = 0x0000013c,
2793 	.hal_sw2reo_ring_hp = 0x00003018,
2796 	.hal_reo_cmd_ring_base_lsb = 0x000000e4,
2797 	.hal_reo_cmd_ring_hp = 0x00003010,
2800 	.hal_reo_status_ring_base_lsb = 0x00000504,
2801 	.hal_reo_status_hp = 0x00003070,
2804 	.hal_seq_wcss_umac_ce0_src_reg = 0x08400000
2806 	.hal_seq_wcss_umac_ce0_dst_reg = 0x08401000
2808 	.hal_seq_wcss_umac_ce1_src_reg = 0x08402000
2810 	.hal_seq_wcss_umac_ce1_dst_reg = 0x08403000
2814 	.hal_wbm_idle_link_ring_base_lsb = 0x00000874,
2815 	.hal_wbm_idle_link_ring_misc = 0x00000884,
2818 	.hal_wbm_release_ring_base_lsb = 0x000001ec,
2821 	.hal_wbm0_release_ring_base_lsb = 0x00000924,
2822 	.hal_wbm1_release_ring_base_lsb = 0x0000097c,