Lines Matching +full:wcn3990 +full:- +full:wifi
1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
123 /* WCN3990 1.0 definitions */
125 #define WCN3990_HW_1_0_FW_DIR ATH10K_FW_DIR "/WCN3990/hw1.0"
131 #define ATH10K_FW_API2_FILE "firmware-2.bin"
132 #define ATH10K_FW_API3_FILE "firmware-3.bin"
135 #define ATH10K_FW_API4_FILE "firmware-4.bin"
138 #define ATH10K_FW_API5_FILE "firmware-5.bin"
140 /* the firmware-6.bin blob */
141 #define ATH10K_FW_API6_FILE "firmware-6.bin"
144 #define ATH10K_FW_UTF_API2_FILE "utf-2.bin"
149 #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K"
150 #define ATH10K_BOARD_MAGIC "QCA-ATH10K-BOARD"
153 #define ATH10K_BOARD_API2_FILE "board-2.bin"
397 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X)
398 #define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887)
399 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174)
400 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0)
401 #define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888)
402 #define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984)
403 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377)
404 #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019)
405 #define QCA_REV_WCN3990(ar) ((ar)->hw_rev == ATH10K_HW_WCN3990)
408 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
409 * - raw have FCS, nwifi doesn't
410 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher
416 /* Native Wifi decap mode is used to align IP frames to 4-byte
417 * boundaries and avoid a very expensive re-alignment in mac80211.
483 ATH10K_HW_REFCLK_UNKNOWN = -1,
587 /* Targets supporting physical addressing capability above 32-bits */
663 if (hw->hw_ops->tx_data_rssi_pad_bytes) in ath10k_tx_data_rssi_get_pad_bytes()
664 return hw->hw_ops->tx_data_rssi_pad_bytes(htt); in ath10k_tx_data_rssi_get_pad_bytes()
672 if (hw->hw_ops->is_rssi_enable) in ath10k_is_rssi_enable()
673 return hw->hw_ops->is_rssi_enable(resp); in ath10k_is_rssi_enable()
752 /* Target specific defines for WMI-TLV firmware */
763 /* Target specific defines for WMI-HL-1.0 firmware */
774 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan
794 /* 100 ms for video, best-effort, and background */
840 #define CE_COUNT ar->hw_values->ce_count
854 #define MSI_ASSIGN_CE_MAX ar->hw_values->msi_assign_ce_max
857 #define RTC_STATE_V_ON ar->hw_values->rtc_state_val_on
867 #define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address
868 #define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address
872 #define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address
877 #define WLAN_MAC_BASE_ADDRESS ar->regs->wlan_mac_base_address
881 #define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address
882 #define CE0_BASE_ADDRESS ar->regs->ce0_base_address
883 #define CE1_BASE_ADDRESS ar->regs->ce1_base_address
884 #define CE2_BASE_ADDRESS ar->regs->ce2_base_address
885 #define CE3_BASE_ADDRESS ar->regs->ce3_base_address
886 #define CE4_BASE_ADDRESS ar->regs->ce4_base_address
887 #define CE5_BASE_ADDRESS ar->regs->ce5_base_address
888 #define CE6_BASE_ADDRESS ar->regs->ce6_base_address
889 #define CE7_BASE_ADDRESS ar->regs->ce7_base_address
892 #define PCIE_LOCAL_BASE_ADDRESS ar->regs->pcie_local_base_address
896 #define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask
897 #define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask
911 #define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address
973 #define PCIE_INTR_CLR_ADDRESS ar->regs->pcie_intr_clr_address
974 #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address
978 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz)
981 #define FW_INDICATOR_ADDRESS ar->regs->fw_indicator_address
987 #define PCIE_INTR_FIRMWARE_MASK ar->regs->pcie_intr_fw_mask
988 #define PCIE_INTR_CE_MASK_ALL ar->regs->pcie_intr_ce_mask_all
1199 #define REGION_ACCESS_SIZE_MASK (REGION_ACCESS_SIZE_LIMIT - 1)