1 /* SPDX-License-Identifier: ISC */
3  * Copyright (c) 2005-2011 Atheros Communications Inc.
4  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
6  * Copyright (c) 2021, 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
29 	/* bits 5-23 currently reserved */
34 enum htt_h2t_msg_type { /* host-to-target */
57 	u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)];
74  * but the host shall use the bit-mast + bit-shift defs, to be endian-
176  * htt_data_tx_desc - used for data tx path
179  *       ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_
241 #define HTT_RX_RING_FILL_LEVEL (((HTT_RX_RING_SIZE) / 2) - 1)
242 #define HTT_RX_RING_FILL_LEVEL_DUAL_MAC (HTT_RX_RING_SIZE - 1)
245 	/* the following offsets are in 4-byte units */
261 	__le16 rx_ring_len; /* in 4-byte words */
262 	__le16 rx_ring_bufsize; /* rx skb size - in bytes */
272 	__le16 rx_ring_len; /* in 4-byte words */
273 	__le16 rx_ring_bufsize; /* rx skb size - in bytes */
296  * htt_stats_req - request target to send specified statistics
300  *	so make sure its little-endian.
302  *	so make sure its little-endian.
305  * @cookie_lsb: used for confirmation message from target->host
326  * htt_oob_sync_req - request out-of-band sync
329  * HTT host-to-target messages until some other target agent locally
334  * This allows other host-target components to synchronize their operation
341  * The HTT target FW will suspend its host->target message processing as long
342  * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128.
368 	u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)];
385 /*=== target -> host messages ===============================================*/
532  * htt_resp_hdr - header for target-to-host messages
544 /* htt_ver_resp - response sent for htt_ver_req */
685 	/* Non-data in promiscuous mode */
761 	ptr += sizeof(rx_ind->hdr)  in htt_rx_ind_get_mpdu_ranges()
762 	     + sizeof(rx_ind->ppdu)  in htt_rx_ind_get_mpdu_ranges()
763 	     + sizeof(rx_ind->prefix)  in htt_rx_ind_get_mpdu_ranges()
764 	     + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4);  in htt_rx_ind_get_mpdu_ranges()
773 	ptr += sizeof(rx_ind->hdr)  in htt_rx_ind_get_mpdu_ranges_hl()
774 	     + sizeof(rx_ind->ppdu)  in htt_rx_ind_get_mpdu_ranges_hl()
775 	     + sizeof(rx_ind->prefix)  in htt_rx_ind_get_mpdu_ranges_hl()
776 	     + sizeof(rx_ind->fw_desc);  in htt_rx_ind_get_mpdu_ranges_hl()
786  * htt_rx_flush - discard or reorder given range of mpdus
789  *	[seq_num_start, seq_num_end-1] are valid.
910  * @brief target -> host TX completion indication message definition
917  *          |-------------------------------------------------------------|
919  *          |-------------------------------------------------------------|
921  *          |-------------------------------------------------------------|
923  *          |-------------------------------------------------------------|
925  *          |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -|
927  *          |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -|
929  *          |-------------------------------------------------------------|
931  *          |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -|
932  *    -msg_type
935  *    -status
939  *    -tid
944  *    -tid_invalid
948  *    -num
952  *    -A0 = append
957  *    -A1 = append1
962  *    -TP = MSDU tx power presence
966  *            The order of the per-MSDU tx power reports matches the order
969  *    -A2 = append2
972  *            TX_COMP_IND message.  The order of the per-MSDU ACK RSSI report
1017 	u32 num_enqued; /* 1 for non-AMPDU */
1126  * target -> host test message definition
1130  * The message consists of a 4-octet header, followed by a variable
1131  * number of 32-bit integer values, followed by a variable number
1132  * of 8-bit character values.
1135  * |-----------------------------------------------------------|
1137  * |-----------------------------------------------------------|
1139  * |-----------------------------------------------------------|
1141  * |-----------------------------------------------------------|
1143  * |-----------------------------------------------------------|
1145  * |-----------------------------------------------------------|
1147  * |-----------------------------------------------------------|
1148  *   - MSG_TYPE
1152  *   - NUM_INTS
1154  *     Purpose: indicate how many 32-bit integers follow the message header
1155  *   - NUM_CHARS
1157  *     Purpose: indicate how many 8-bit characters follow the series of integers
1165 	 *  b) num_chars * sizeof(u8) aligned to 4bytes
1172 	return (__le32 *)rx_test->payload;  in htt_rx_test_get_ints()
1177 	return rx_test->payload + (rx_test->num_ints * sizeof(__le32));  in htt_rx_test_get_chars()
1181  * target -> host packet log message
1185  * The message consists of a 4-octet header,followed by a variable number
1186  * of 32-bit character values.
1189  * |-----------------------------------------------------------|
1191  * |-----------------------------------------------------------|
1193  * |-----------------------------------------------------------|
1194  *   - MSG_TYPE
1208 	/* MPDUs received in-order */
1223 	/* MPDUs dropped due to monitor mode non-data packet */
1316 	/* Cnts any change in ring routing mid-ppdu */
1322 	/* Extra frags on rings 0-3 */
1345 	/* Number of mpdu errors - FCS, MIC, ENC etc. */
1371  * htt_dbg_stats_status -
1372  * present -     The requested stats have been delivered in full.
1377  * partial -     The requested stats have been delivered in part.
1381  * error -       The requested stats could not be delivered, for example due
1384  * invalid -     The requested stat type is either not recognized, or the
1386  * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1387  * series_done - This special value indicates that no further stats info
1400  * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank
1416  * |------------------------------------------------------------|
1418  * |------------------------------------------------------------|
1420  * |------------------------------------------------------------|
1422  * |------------------------------------------------------------|
1424  * |------------------------------------------------------------|
1426  * |------------------------------------------------------------|
1428  * |------------------------------------------------------------|
1430  * |------------------------------------------------------------|
1432  *  - MSG_TYPE
1435  *  - BANKx_BASE_ADDRESS
1439  *  - BANKx_MIN_ID
1443  *  - BANKx_MAX_ID
1477  * struct htt_q_state_conf - part of htt_frag_desc_bank_cfg for host q state config
1485  *	however firmware (at least 10.4.3-00191) ignores this host
1489  * @pad: struct padding for 32-bit alignment
1525  * struct htt_q_state - shared between host and firmware via DMA
1529  * performance. This is most notably used for MU-MIMO aggregation when multiple
1530  * MU clients are connected.
1578 	return (void *)&ind->records[le16_to_cpu(ind->num_records)];  in ath10k_htt_get_tx_fetch_ind_resp_ids()
1676 	/* WEP: 24-bit PN */
1679 	/* TKIP or CCMP: 48-bit PN */
1682 	/* WAPI: 128-bit PN */
1733 /*** host side structures follow ***/
1789 		 * Ring of network buffer objects - This ring is
1804 		 * pointing to specific (re-ordered) buffers.
1813 		 * Ring of buffer addresses -
1832 		/* size - 1 */
1842 		 * alloc_idx - where HTT SW has deposited empty buffers
1858 		 * refill_retry_timer - timer triggered when the ring is
1877 	/* FIFO for storing tx done status {ack, no-ack, discard} and msdu id */
1880 	/* set if host-fw communication goes haywire
1951 	if (!htt->tx_ops->htt_send_rx_ring_cfg)  in ath10k_htt_send_rx_ring_cfg()
1952 		return -EOPNOTSUPP;  in ath10k_htt_send_rx_ring_cfg()
1954 	return htt->tx_ops->htt_send_rx_ring_cfg(htt);  in ath10k_htt_send_rx_ring_cfg()
1959 	if (!htt->tx_ops->htt_send_frag_desc_bank_cfg)  in ath10k_htt_send_frag_desc_bank_cfg()
1960 		return -EOPNOTSUPP;  in ath10k_htt_send_frag_desc_bank_cfg()
1962 	return htt->tx_ops->htt_send_frag_desc_bank_cfg(htt);  in ath10k_htt_send_frag_desc_bank_cfg()
1967 	if (!htt->tx_ops->htt_alloc_frag_desc)  in ath10k_htt_alloc_frag_desc()
1968 		return -EOPNOTSUPP;  in ath10k_htt_alloc_frag_desc()
1970 	return htt->tx_ops->htt_alloc_frag_desc(htt);  in ath10k_htt_alloc_frag_desc()
1975 	if (htt->tx_ops->htt_free_frag_desc)  in ath10k_htt_free_frag_desc()
1976 		htt->tx_ops->htt_free_frag_desc(htt);  in ath10k_htt_free_frag_desc()
1983 	return htt->tx_ops->htt_tx(htt, txmode, msdu);  in ath10k_htt_tx()
1988 	if (htt->tx_ops->htt_flush_tx)  in ath10k_htt_flush_tx()
1989 		htt->tx_ops->htt_flush_tx(htt);  in ath10k_htt_flush_tx()
1994 	if (!htt->tx_ops->htt_alloc_txbuff)  in ath10k_htt_alloc_txbuff()
1995 		return -EOPNOTSUPP;  in ath10k_htt_alloc_txbuff()
1997 	return htt->tx_ops->htt_alloc_txbuff(htt);  in ath10k_htt_alloc_txbuff()
2002 	if (htt->tx_ops->htt_free_txbuff)  in ath10k_htt_free_txbuff()
2003 		htt->tx_ops->htt_free_txbuff(htt);  in ath10k_htt_free_txbuff()
2011 	if (!htt->tx_ops->htt_h2t_aggr_cfg_msg)  in ath10k_htt_h2t_aggr_cfg_msg()
2012 		return -EOPNOTSUPP;  in ath10k_htt_h2t_aggr_cfg_msg()
2014 	return htt->tx_ops->htt_h2t_aggr_cfg_msg(htt,  in ath10k_htt_h2t_aggr_cfg_msg()
2033 	if (!htt->rx_ops->htt_get_rx_ring_size)  in ath10k_htt_get_rx_ring_size()
2036 	return htt->rx_ops->htt_get_rx_ring_size(htt);  in ath10k_htt_get_rx_ring_size()
2042 	if (htt->rx_ops->htt_config_paddrs_ring)  in ath10k_htt_config_paddrs_ring()
2043 		htt->rx_ops->htt_config_paddrs_ring(htt, vaddr);  in ath10k_htt_config_paddrs_ring()
2050 	if (htt->rx_ops->htt_set_paddrs_ring)  in ath10k_htt_set_paddrs_ring()
2051 		htt->rx_ops->htt_set_paddrs_ring(htt, paddr, idx);  in ath10k_htt_set_paddrs_ring()
2056 	if (!htt->rx_ops->htt_get_vaddr_ring)  in ath10k_htt_get_vaddr_ring()
2059 	return htt->rx_ops->htt_get_vaddr_ring(htt);  in ath10k_htt_get_vaddr_ring()
2064 	if (htt->rx_ops->htt_reset_paddrs_ring)  in ath10k_htt_reset_paddrs_ring()
2065 		htt->rx_ops->htt_reset_paddrs_ring(htt, idx);  in ath10k_htt_reset_paddrs_ring()
2072 	if (!htt->rx_ops->htt_rx_proc_rx_frag_ind)  in ath10k_htt_rx_proc_rx_frag_ind()
2075 	return htt->rx_ops->htt_rx_proc_rx_frag_ind(htt, rx, skb);  in ath10k_htt_rx_proc_rx_frag_ind()
2188 	if (hw->rx_desc_ops->rx_desc_get_l3_pad_bytes)  in ath10k_htt_rx_desc_get_l3_pad_bytes()
2189 		return hw->rx_desc_ops->rx_desc_get_l3_pad_bytes(rxd);  in ath10k_htt_rx_desc_get_l3_pad_bytes()
2196 	if (hw->rx_desc_ops->rx_desc_get_msdu_limit_error)  in ath10k_htt_rx_desc_msdu_limit_error()
2197 		return hw->rx_desc_ops->rx_desc_get_msdu_limit_error(rxd);  in ath10k_htt_rx_desc_msdu_limit_error()
2210 	if (hw->rx_desc_ops->rx_desc_from_raw_buffer)  in ath10k_htt_rx_desc_from_raw_buffer()
2211 		return hw->rx_desc_ops->rx_desc_from_raw_buffer(buff);  in ath10k_htt_rx_desc_from_raw_buffer()
2212 	return &((struct htt_rx_desc_v1 *)buff)->base;  in ath10k_htt_rx_desc_from_raw_buffer()
2219 	if (hw->rx_desc_ops->rx_desc_get_offsets) {  in ath10k_htt_rx_desc_get_offsets()
2220 		hw->rx_desc_ops->rx_desc_get_offsets(off);  in ath10k_htt_rx_desc_get_offsets()
2223 		off->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status));  in ath10k_htt_rx_desc_get_offsets()
2224 		off->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload));  in ath10k_htt_rx_desc_get_offsets()
2225 		off->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start));  in ath10k_htt_rx_desc_get_offsets()
2226 		off->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end));  in ath10k_htt_rx_desc_get_offsets()
2227 		off->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start));  in ath10k_htt_rx_desc_get_offsets()
2228 		off->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end));  in ath10k_htt_rx_desc_get_offsets()
2229 		off->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start));  in ath10k_htt_rx_desc_get_offsets()
2230 		off->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end));  in ath10k_htt_rx_desc_get_offsets()
2231 		off->rx_attention_offset = __cpu_to_le16(desc_offset(attention));  in ath10k_htt_rx_desc_get_offsets()
2232 		off->frag_info_offset =	__cpu_to_le16(desc_offset(frag_info));  in ath10k_htt_rx_desc_get_offsets()
2242 	if (hw->rx_desc_ops->rx_desc_get_attention)  in ath10k_htt_rx_desc_get_attention()
2243 		return hw->rx_desc_ops->rx_desc_get_attention(rxd);  in ath10k_htt_rx_desc_get_attention()
2246 	return &rx_desc->attention;  in ath10k_htt_rx_desc_get_attention()
2254 	if (hw->rx_desc_ops->rx_desc_get_frag_info)  in ath10k_htt_rx_desc_get_frag_info()
2255 		return hw->rx_desc_ops->rx_desc_get_frag_info(rxd);  in ath10k_htt_rx_desc_get_frag_info()
2258 	return &rx_desc->frag_info.common;  in ath10k_htt_rx_desc_get_frag_info()
2266 	if (hw->rx_desc_ops->rx_desc_get_mpdu_start)  in ath10k_htt_rx_desc_get_mpdu_start()
2267 		return hw->rx_desc_ops->rx_desc_get_mpdu_start(rxd);  in ath10k_htt_rx_desc_get_mpdu_start()
2270 	return &rx_desc->mpdu_start;  in ath10k_htt_rx_desc_get_mpdu_start()
2278 	if (hw->rx_desc_ops->rx_desc_get_mpdu_end)  in ath10k_htt_rx_desc_get_mpdu_end()
2279 		return hw->rx_desc_ops->rx_desc_get_mpdu_end(rxd);  in ath10k_htt_rx_desc_get_mpdu_end()
2282 	return &rx_desc->mpdu_end;  in ath10k_htt_rx_desc_get_mpdu_end()
2290 	if (hw->rx_desc_ops->rx_desc_get_msdu_start)  in ath10k_htt_rx_desc_get_msdu_start()
2291 		return hw->rx_desc_ops->rx_desc_get_msdu_start(rxd);  in ath10k_htt_rx_desc_get_msdu_start()
2294 	return &rx_desc->msdu_start.common;  in ath10k_htt_rx_desc_get_msdu_start()
2302 	if (hw->rx_desc_ops->rx_desc_get_msdu_end)  in ath10k_htt_rx_desc_get_msdu_end()
2303 		return hw->rx_desc_ops->rx_desc_get_msdu_end(rxd);  in ath10k_htt_rx_desc_get_msdu_end()
2306 	return &rx_desc->msdu_end.common;  in ath10k_htt_rx_desc_get_msdu_end()
2314 	if (hw->rx_desc_ops->rx_desc_get_ppdu_start)  in ath10k_htt_rx_desc_get_ppdu_start()
2315 		return hw->rx_desc_ops->rx_desc_get_ppdu_start(rxd);  in ath10k_htt_rx_desc_get_ppdu_start()
2318 	return &rx_desc->ppdu_start;  in ath10k_htt_rx_desc_get_ppdu_start()
2326 	if (hw->rx_desc_ops->rx_desc_get_ppdu_end)  in ath10k_htt_rx_desc_get_ppdu_end()
2327 		return hw->rx_desc_ops->rx_desc_get_ppdu_end(rxd);  in ath10k_htt_rx_desc_get_ppdu_end()
2330 	return &rx_desc->ppdu_end.common;  in ath10k_htt_rx_desc_get_ppdu_end()
2338 	if (hw->rx_desc_ops->rx_desc_get_rx_hdr_status)  in ath10k_htt_rx_desc_get_rx_hdr_status()
2339 		return hw->rx_desc_ops->rx_desc_get_rx_hdr_status(rxd);  in ath10k_htt_rx_desc_get_rx_hdr_status()
2342 	return rx_desc->rx_hdr_status;  in ath10k_htt_rx_desc_get_rx_hdr_status()
2350 	if (hw->rx_desc_ops->rx_desc_get_msdu_payload)  in ath10k_htt_rx_desc_get_msdu_payload()
2351 		return hw->rx_desc_ops->rx_desc_get_msdu_payload(rxd);  in ath10k_htt_rx_desc_get_msdu_payload()
2354 	return rx_desc->msdu_payload;  in ath10k_htt_rx_desc_get_msdu_payload()
2396 	return HTT_RX_BUF_SIZE - (int)hw->rx_desc_ops->rx_desc_size;  in ath10k_htt_rx_msdu_size()
2410 #define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1)