Lines Matching +full:enable +full:- +full:modem +full:- +full:interrupt
1 /* SPDX-License-Identifier: GPL-2.0 */
5 /* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
24 #define DMER 0x09 /* DMA Master Enable */
27 /* Interrupt registers */
28 #define ISR0 0x10 /* Interrupt Status 0 */
29 #define ISR1 0x11 /* Interrupt Status 1 */
30 #define ISR2 0x12 /* Interrupt Status 2 */
32 #define IER0 0x14 /* Interrupt Enable 0 */
33 #define IER1 0x15 /* Interrupt Enable 1 */
34 #define IER2 0x16 /* Interrupt Enable 2 */
36 #define ITCR 0x18 /* Interrupt Control */
37 #define IVR 0x1A /* Interrupt Vector */
38 #define IMVR 0x1C /* Interrupt Modified Vector */
42 /* MSCI channel (port) 0 registers - offset 0x20
43 MSCI channel (port) 1 registers - offset 0x40 */
55 #define IE0 0x08 /* Interrupt Enable 0 */
56 #define IE1 0x09 /* Interrupt Enable 1 */
57 #define IE2 0x0A /* Interrupt Enable 2 */
58 #define FIE 0x0B /* Frame Interrupt Enable */
77 /* Timer channel 0 (port 0 RX) registers - offset 0x60
78 Timer channel 1 (port 0 TX) registers - offset 0x68
79 Timer channel 2 (port 1 RX) registers - offset 0x70
80 Timer channel 3 (port 1 TX) registers - offset 0x78
88 #define TCNTL 0x00 /* Up-counter L */
89 #define TCNTH 0x01 /* Up-counter H */
97 /* DMA channel 0 (port 0 RX) registers - offset 0x80
98 DMA channel 1 (port 0 TX) registers - offset 0xA0
99 DMA channel 2 (port 1 RX) registers - offset 0xC0
100 DMA channel 3 (port 1 TX) registers - offset 0xE0
136 #define FCT 0x13 /* Frame End Interrupt Counter */
139 #define DIR 0x14 /* DMA Interrupt Enable */
156 u8 unused; /* pads to 2-byte boundary */
175 #define DIR_EOME 0x40 /* Frame Transfer Completed (chained-block) */
176 #define DIR_BOFE 0x20 /* Buffer Overflow/Underflow (chained-block)*/
177 #define DIR_COFE 0x10 /* Counter Overflow (chained-block) */
181 #define DSR_EOM 0x40 /* Frame Transfer Completed (chained-block) */
182 #define DSR_BOF 0x20 /* Buffer Overflow/Underflow (chained-block)*/
183 #define DSR_COF 0x10 /* Counter Overflow (chained-block) */
184 #define DSR_DE 0x02 /* DMA Enable */
187 /* DMA Master Enable Register (DMER) bits */
188 #define DMER_DME 0x80 /* DMA Master Enable */
195 #define MD0_HDLC 0x80 /* Bit-sync HDLC mode */
196 #define MD0_CRC_ENA 0x04 /* Enable CRC code calculation */
197 #define MD0_CRC_CCITT 0x02 /* CCITT CRC instead of CRC-16 */
198 #define MD0_CRC_PR1 0x01 /* Initial all-ones instead of all-zeros */
223 #define ST3_CTS 0x08 /* modem input - /CTS */
224 #define ST3_DCD 0x04 /* modem input - /DCD */
226 #define IE0_TXINT 0x80 /* TX INT MSCI interrupt enable */
227 #define IE0_RXINTA 0x40 /* RX INT A MSCI interrupt enable */
228 #define IE1_UDRN 0x80 /* TX underrun MSCI interrupt enable */
232 #define DCR_CLEAR_EOF 0x02 /* Clear EOF interrupt */
234 /* TX and RX Clock Source - RXS and TXS */