Lines Matching +full:0 +full:x0543
82 module_param(fst_txq_low, int, 0);
83 module_param(fst_txq_high, int, 0);
84 module_param(fst_max_reads, int, 0);
85 module_param(fst_excluded_cards, int, 0);
86 module_param_array(fst_excluded_list, int, NULL, 0);
105 #define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */
107 #define SMC_BASE 0x00002000L /* Base offset of the shared memory window main
110 #define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA
159 /* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */
166 #define DMA_OWN 0x80 /* SmartDMA owns the descriptor */
167 #define TX_STP 0x02 /* Tx: start of packet */
168 #define TX_ENP 0x01 /* Tx: end of packet */
169 #define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */
170 #define RX_FRAM 0x20 /* Rx: framing error */
171 #define RX_OFLO 0x10 /* Rx: overflow error */
172 #define RX_CRC 0x08 /* Rx: CRC error */
173 #define RX_HBUF 0x04 /* Rx: buffer error */
174 #define RX_STP 0x02 /* Rx: start of packet */
175 #define RX_ENP 0x01 /* Rx: end of packet */
191 #define CTLA_CHG 0x18 /* Control signal changed */
192 #define CTLB_CHG 0x19
193 #define CTLC_CHG 0x1A
194 #define CTLD_CHG 0x1B
196 #define INIT_CPLT 0x20 /* Initialisation complete */
197 #define INIT_FAIL 0x21 /* Initialisation failed */
199 #define ABTA_SENT 0x24 /* Abort sent */
200 #define ABTB_SENT 0x25
201 #define ABTC_SENT 0x26
202 #define ABTD_SENT 0x27
204 #define TXA_UNDF 0x28 /* Transmission underflow */
205 #define TXB_UNDF 0x29
206 #define TXC_UNDF 0x2A
207 #define TXD_UNDF 0x2B
209 #define F56_INT 0x2C
210 #define M32_INT 0x2D
212 #define TE1_ALMA 0x30
218 u8 internalClock; /* 1 => internal clock, 0 => external */
219 u8 transparentMode; /* 1 => on, 0 => off */
220 u8 invertClock; /* 0 => normal, 1 => inverted */
276 u8 taskStatus; /* 0x00 => initialising, 0x01 => running,
277 * 0xFF => halted
280 u8 interruptHandshake; /* Set to 0x01 by adapter to signal interrupt,
281 * set to 0xEE by host to acknowledge interrupt
286 u32 smcFirmwareVersion; /* 0xIIVVRRBB where II = product ID, VV = major
308 u16 clockStatus[FST_MAX_PORTS]; /* lsb: 0=> present, 1=> absent */
310 u16 cableStatus; /* lsb: 0=> present, 1=> absent */
347 * Bit 0: 1 enables LED identify mode
363 #define END_SIG 0x12345678
366 #define NOP 0 /* No operation */
375 #define CNTRL_9052 0x50 /* Control Register */
376 #define CNTRL_9054 0x6c /* Control Register */
378 #define INTCSR_9052 0x4c /* Interrupt control/status register */
379 #define INTCSR_9054 0x68 /* Interrupt control/status register */
382 /* Note that we will be using DMA Channel 0 for copying rx data
385 #define DMAMODE0 0x80
386 #define DMAPADR0 0x84
387 #define DMALADR0 0x88
388 #define DMASIZ0 0x8c
389 #define DMADPR0 0x90
390 #define DMAMODE1 0x94
391 #define DMAPADR1 0x98
392 #define DMALADR1 0x9c
393 #define DMASIZ1 0xa0
394 #define DMADPR1 0xa4
395 #define DMACSR0 0xa8
396 #define DMACSR1 0xa9
397 #define DMAARB 0xac
398 #define DMATHR 0xb0
399 #define DMADAC0 0xb4
400 #define DMADAC1 0xb8
401 #define DMAMARBR 0xac
404 #define FST_RX_DMA_INT 0x01
405 #define FST_TX_DMA_INT 0x02
406 #define FST_CARD_INT 0x04
515 } while (0)
519 if (0) \
521 } while (0)
528 PCI_ANY_ID, 0, 0, FST_TYPE_T2P},
531 PCI_ANY_ID, 0, 0, FST_TYPE_T4P},
534 PCI_ANY_ID, 0, 0, FST_TYPE_T1U},
537 PCI_ANY_ID, 0, 0, FST_TYPE_T2U},
540 PCI_ANY_ID, 0, 0, FST_TYPE_T4U},
543 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
546 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
547 {0,} /* End */
607 fst_work_txq = 0; in fst_process_tx_work_q()
612 for (i = 0; i < FST_MAX_CARDS; i++) { in fst_process_tx_work_q()
613 if (work_txq & 0x01) { in fst_process_tx_work_q()
635 fst_work_intq = 0; in fst_process_int_work_q()
640 for (i = 0; i < FST_MAX_CARDS; i++) { in fst_process_int_work_q()
641 if (work_intq & 0x01) { in fst_process_int_work_q()
678 outw(0x440f, card->pci_conf + CNTRL_9054 + 2); in fst_cpureset()
679 outw(0x040f, card->pci_conf + CNTRL_9054 + 2); in fst_cpureset()
683 outw(0x240f, card->pci_conf + CNTRL_9054 + 2); in fst_cpureset()
687 outw(0x040f, card->pci_conf + CNTRL_9054 + 2); in fst_cpureset()
698 outl(regval | 0x40000000, card->pci_conf + CNTRL_9052); in fst_cpureset()
699 outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052); in fst_cpureset()
716 outw(0x040e, card->pci_conf + CNTRL_9054 + 2); in fst_cpurelease()
717 outw(0x040f, card->pci_conf + CNTRL_9054 + 2); in fst_cpurelease()
733 outw(0x0543, card->pci_conf + INTCSR_9052); in fst_clear_intr()
743 outl(0x0f0c0900, card->pci_conf + INTCSR_9054); in fst_enable_intr()
745 outw(0x0543, card->pci_conf + INTCSR_9052); in fst_enable_intr()
754 outl(0x00000000, card->pci_conf + INTCSR_9054); in fst_disable_intr()
756 outw(0x0000, card->pci_conf + INTCSR_9052); in fst_disable_intr()
788 outl(0x00020441, card->pci_conf + DMAMODE0); in fst_init_dma()
789 outl(0x00020441, card->pci_conf + DMAMODE1); in fst_init_dma()
790 outl(0x0, card->pci_conf + DMATHR); in fst_init_dma()
870 outl(0x00000000c, card->pci_conf + DMADPR0); /* In this direction */ in fst_rx_dma()
875 outb(0x03, card->pci_conf + DMACSR0); /* Start the transfer */ in fst_rx_dma()
893 outl(0x000000004, card->pci_conf + DMADPR1); /* In this direction */ in fst_tx_dma()
898 outb(0x03, card->pci_conf + DMACSR1); /* Start the transfer */ in fst_tx_dma()
915 mbval = FST_RDW(card, portMailbox[port->index][0]); in fst_issue_cmd()
917 safety = 0; in fst_issue_cmd()
929 mbval = FST_RDW(card, portMailbox[port->index][0]); in fst_issue_cmd()
931 if (safety > 0) in fst_issue_cmd()
937 FST_WRW(card, portMailbox[port->index][0], cmd); in fst_issue_cmd()
940 port->txpos = 0; in fst_issue_cmd()
941 port->txipos = 0; in fst_issue_cmd()
942 port->start = 0; in fst_issue_cmd()
984 for (i = 0; i < NUM_RX_BUFFER; i++) { in fst_rx_config()
985 offset = BUF_OFFSET(rxBuffer[pi][i][0]); in fst_rx_config()
993 port->rxpos = 0; in fst_rx_config()
1011 for (i = 0; i < NUM_TX_BUFFER; i++) { in fst_tx_config()
1012 offset = BUF_OFFSET(txBuffer[pi][i][0]); in fst_tx_config()
1016 FST_WRW(card, txDescrRing[pi][i].bcnt, 0); in fst_tx_config()
1017 FST_WRB(card, txDescrRing[pi][i].bits, 0); in fst_tx_config()
1019 port->txpos = 0; in fst_tx_config()
1020 port->txipos = 0; in fst_tx_config()
1021 port->start = 0; in fst_tx_config()
1139 i = 0; in fst_recover_rx_error()
1140 while ((dmabits & (DMA_OWN | RX_STP)) == 0) { in fst_recover_rx_error()
1190 if (len == 0) { in fst_intr_rx()
1194 pr_err("Frame received with 0 length. Card %d Port %d\n", in fst_intr_rx()
1237 card->mem + BUF_OFFSET(rxBuffer[pi][rxp][0]), in fst_intr_rx()
1263 BUF_OFFSET(rxBuffer[pi][rxp][0]), len); in fst_intr_rx()
1292 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) { in do_bottom_half_tx()
1306 if (txq_length < 0) { in do_bottom_half_tx()
1313 if (txq_length > 0) { in do_bottom_half_tx()
1320 port->txqs = 0; in do_bottom_half_tx()
1334 txpos][0]), in do_bottom_half_tx()
1353 [port->txpos][0]), in do_bottom_half_tx()
1357 port->txpos = 0; in do_bottom_half_tx()
1364 port->start = 0; in do_bottom_half_tx()
1382 int rx_count = 0; in do_bottom_half_rx()
1386 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) { in do_bottom_half_rx()
1417 unsigned int dma_intcsr = 0; in fst_intr()
1443 do_card_interrupt = 0; in fst_intr()
1447 FST_WRB(card, interruptHandshake, 0xEE); in fst_intr()
1453 if (dma_intcsr & 0x00200000) { in fst_intr()
1454 /* DMA Channel 0 (Rx transfer complete) in fst_intr()
1457 outb(0x8, card->pci_conf + DMACSR0); in fst_intr()
1461 card->dmarx_in_progress = 0; in fst_intr()
1464 if (dma_intcsr & 0x00400000) { in fst_intr()
1468 outb(0x8, card->pci_conf + DMACSR1); in fst_intr()
1471 card->dmatx_in_progress = 0; in fst_intr()
1482 FST_WRL(card, interruptRetryCount, 0); in fst_intr()
1493 rdidx = FST_RDB(card, interruptEvent.rdindex) & 0x1f; in fst_intr()
1494 wridx = FST_RDB(card, interruptEvent.wrindex) & 0x1f; in fst_intr()
1497 port = &card->ports[event & 0x03]; in fst_intr()
1553 rdidx = 0; in fst_intr()
1579 /* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */ in check_started_ok()
1581 if (i == 0x01) { in check_started_ok()
1583 } else if (i == 0xFF) { in check_started_ok()
1587 } else if (i != 0x00) { in check_started_ok()
1588 pr_err("Unknown firmware status 0x%x\n", i); in check_started_ok()
1615 err = 0; in set_conf_from_info()
1660 FST_WRB(card, suConfig.enableIdleCode, 0); in set_conf_from_info()
1699 memset(info, 0, sizeof(struct fstioc_info)); in gather_conf_info()
1733 * in bits 0 and 1 of cableStatus. See which port we are and in gather_conf_info()
1737 if (port->index == 0) { in gather_conf_info()
1768 info->idleCode = 0; in gather_conf_info()
1854 return 0; in fst_set_iface()
1890 return 0; /* only type requested */ in fst_get_iface()
1896 memset(&sync, 0, sizeof(sync)); in fst_get_iface()
1901 sync.loopback = 0; in fst_get_iface()
1907 return 0; in fst_get_iface()
1932 return 0; in fst_siocdevprivate()
1937 return 0; in fst_siocdevprivate()
1973 return 0; in fst_siocdevprivate()
1987 FST_WRB(card, interruptHandshake, 0xEE); in fst_siocdevprivate()
2000 return 0; in fst_siocdevprivate()
2050 return 0; in fst_ioctl()
2055 return 0; in fst_ioctl()
2080 port->run = 0; in fst_openport()
2097 port->txqe = 0; in fst_openport()
2098 port->txqs = 0; in fst_openport()
2107 port->run = 0; in fst_closeport()
2137 return 0; in fst_open()
2164 return 0; in fst_close()
2174 return 0; in fst_attach()
2193 port->start = 0; in fst_tx_timeout()
2234 if (txq_length < 0) { in fst_start_xmit()
2265 port->txqe = 0; in fst_start_xmit()
2301 for (i = 0; i < card->nports; i++) { in fst_init_card()
2303 if (err < 0) { in fst_init_card()
2313 port_to_dev(&card->ports[0])->name, in fst_init_card()
2316 return 0; in fst_init_card()
2329 * Returns 0 to indicate success, or errno otherwise.
2336 int err = 0; in fst_add_one()
2348 if (fst_excluded_cards != 0) { in fst_add_one()
2352 for (i = 0; i < fst_excluded_cards; i++) { in fst_add_one()
2389 card->ctlmem = ioremap(card->phys_ctlmem, 0x10); in fst_add_one()
2420 for (i = 0; i < card->nports; i++) { in fst_add_one()
2434 card->ports[i].run = 0; in fst_add_one()
2444 + BUF_OFFSET(txBuffer[i][0][0]); in fst_add_one()
2505 return 0; /* Success */ in fst_add_one()
2512 for (i = 0 ; i < card->nports ; i++) in fst_add_one()
2517 for (i = 0 ; i < card->nports ; i++) in fst_add_one()
2544 for (i = 0; i < card->nports; i++) { in fst_remove_one()
2583 for (i = 0; i < FST_MAX_CARDS; i++) in fst_init()