4  * Copyright (C) 2008-2024, VMware, Inc. All Rights Reserved.
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23  * Maintained by: pv-[email protected]
73 #define VMXNET3_REG_ALIGN       8	/* All registers are 8-byte aligned. */
133  *	Little Endian layout of bitfields -
135  *	Byte 1 :	oco gen 13.len.8
137  *	Byte 3 : 	13...msscof...6
139  *	Big Endian layout of bitfields -
142  *	Byte 2 :	oco gen 13.len.8
143  *	Byte 3 :	7.....len.....0
158 	u32 gen:1;      /* generation bit */  member
162 	u32 gen:1;      /* generation bit */  member
192 #define VMXNET3_OM_TSO          3
198 #define VMXNET3_TXD_EOP_DWORD_SHIFT 3
218 #define VMXNET3_TCD_GEN_DWORD_SHIFT	3
229 	u32		gen:1;        /* generation bit */  member
236 	u32		gen:1;        /* Generation bit */  member
246 	u32		gen:1;        /* Generation bit */  member
265 	u64  pad:3;
318 	u32		gen:1;        /* generation bit */  member
340 	u32		gen:1;        /* generation bit */  member
351 	u32		gen:1;        /* generation bit */  member
373 	u32		gen:1;        /* generation bit */  member
378 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */
396 #define VMXNET3_RCD_RSS_TYPE_IPV6     3
422 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
425 /* max # of tx descs for a non-tso pkt */
431 #define VMXNET3_MAX_RX_BUF_SIZE  ((1 << 14) - 1)
438 #define VMXNET3_RING_BA_MASK    (VMXNET3_RING_BA_ALIGN - 1)
442 #define VMXNET3_RING_SIZE_MASK  (VMXNET3_RING_SIZE_ALIGN - 1)
446 #define VMXNET3_TXDATA_DESC_SIZE_MASK  (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1)
450 #define VMXNET3_RXDATA_DESC_SIZE_MASK  (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1)
454 #define VMXNET3_RXTS_DESC_SIZE_MASK  (VMXNET3_RXTS_DESC_SIZE_ALIGN - 1)
457 #define VMXNET3_TXTS_DESC_SIZE_MASK  (VMXNET3_TXTS_DESC_SIZE_ALIGN - 1)
489 #define VMXNET3_CDTYPE_RXCOMP      3    /* Rx Completion Descriptor */
506 	u32		gosBits:2;    /* 32-bit or 64-bit? */
508 	u32		gosBits:2;     /* 32-bit or 64-bit? */
596 	u16     pad[3];
609 	VMXNET3_IT_MSIX = 3
648 	u8              reserved2[3];
657 	u8		_pad[3];
759 	VMXNET3_COALESCE_RBC        = 3
792 	__le16					pad[3];
824 	/* read-only region for device, read by dev in response to a SET cmd */
834 	/* read-only region for device, read by dev in response to a SET cmd */
860 #define VMXNET3_ECR_DIC         (1 << 3)
863 /* flip the gen bit of a ring */
864 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)  argument
866 /* only use this if moving the idx won't affect the gen bit */
894 #define VMXNET3_CAP_GENEVE_TSO                     3    /* bit 3 of DCR 0 */