4  * Copyright (C) 2008-2024, VMware, Inc. All Rights Reserved.
8  * Free Software Foundation; version 2 of the License and no later version.
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23  * Maintained by: pv-[email protected]
57 	VMXNET3_REG_RXPROD2	= 0xA00	 /* Rx Producer Index for ring 2 */
64 	VMXNET3_REG_LB_RXPROD2  = 0x1800, /* Rx Producer Index for ring 2 */
73 #define VMXNET3_REG_ALIGN       8	/* All registers are 8-byte aligned. */
133  *	Little Endian layout of bitfields -
135  *	Byte 1 :	oco gen 13.len.8
136  *	Byte 2 : 	5.msscof.0 ext1  dtype
139  *	Big Endian layout of bitfields -
142  *	Byte 2 :	oco gen 13.len.8
158 	u32 gen:1;      /* generation bit */  member
162 	u32 gen:1;      /* generation bit */  member
175 	u32 om:2;       /* offload mode */
179 	u32 om:2;       /* offload mode */
191 #define VMXNET3_OM_CSUM         2
199 #define VMXNET3_TXD_GEN_DWORD_SHIFT 2
229 	u32		gen:1;        /* generation bit */  member
236 	u32		gen:1;        /* Generation bit */  member
246 	u32		gen:1;        /* Generation bit */  member
287 	u32		ext1:2;       /* bit 0: indicating v4/v6/.. is for inner header */
292 	u32		ext1:2;       /* bit 0: indicating v4/v6/.. is for inner header */
318 	u32		gen:1;        /* generation bit */  member
340 	u32		gen:1;        /* generation bit */  member
351 	u32		gen:1;        /* generation bit */  member
373 	u32		gen:1;        /* generation bit */  member
395 #define VMXNET3_RCD_RSS_TYPE_TCPIPV4  2
406 	__le64				qword[2];
422 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
425 /* max # of tx descs for a non-tso pkt */
431 #define VMXNET3_MAX_RX_BUF_SIZE  ((1 << 14) - 1)
438 #define VMXNET3_RING_BA_MASK    (VMXNET3_RING_BA_ALIGN - 1)
442 #define VMXNET3_RING_SIZE_MASK  (VMXNET3_RING_SIZE_ALIGN - 1)
446 #define VMXNET3_TXDATA_DESC_SIZE_MASK  (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1)
450 #define VMXNET3_RXDATA_DESC_SIZE_MASK  (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1)
454 #define VMXNET3_RXTS_DESC_SIZE_MASK  (VMXNET3_RXTS_DESC_SIZE_ALIGN - 1)
457 #define VMXNET3_TXTS_DESC_SIZE_MASK  (VMXNET3_TXTS_DESC_SIZE_ALIGN - 1)
495 	VMXNET3_GOS_BITS_64     = 2,
506 	u32		gosBits:2;    /* 32-bit or 64-bit? */
508 	u32		gosBits:2;     /* 32-bit or 64-bit? */
567 	__le64		rxRingBasePA[2];
571 	__le32		rxRingSize[2];   /* # of rx desc */
602 	VMXNET3_IMM_LAZY   = 2
608 	VMXNET3_IT_MSI  = 2,
635 	__le32		reserved[2];
758 	VMXNET3_COALESCE_STATIC     = 2,
820 	__le64					data[2];
824 	/* read-only region for device, read by dev in response to a SET cmd */
834 	/* read-only region for device, read by dev in response to a SET cmd */
859 #define VMXNET3_ECR_LINK        (1 << 2)
863 /* flip the gen bit of a ring */
864 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)  argument
866 /* only use this if moving the idx won't affect the gen bit */
893 #define VMXNET3_CAP_GENEVE_CHECKSUM_OFFLOAD        2    /* bit 2 of DCR 0 */