Lines Matching +full:0 +full:x80000007
35 VMXNET3_REG_VRRS = 0x0, /* Vmxnet3 Revision Report Selection */
36 VMXNET3_REG_UVRS = 0x8, /* UPT Version Report Selection */
37 VMXNET3_REG_DSAL = 0x10, /* Driver Shared Address Low */
38 VMXNET3_REG_DSAH = 0x18, /* Driver Shared Address High */
39 VMXNET3_REG_CMD = 0x20, /* Command */
40 VMXNET3_REG_MACL = 0x28, /* MAC Address Low */
41 VMXNET3_REG_MACH = 0x30, /* MAC Address High */
42 VMXNET3_REG_ICR = 0x38, /* Interrupt Cause Register */
43 VMXNET3_REG_ECR = 0x40, /* Event Cause Register */
44 VMXNET3_REG_DCR = 0x48, /* Device capability register,
45 * from 0x48 to 0x80
47 VMXNET3_REG_PTCR = 0x88, /* Passthru capbility register
48 * from 0x88 to 0xb0
52 /* BAR 0 */
54 VMXNET3_REG_IMR = 0x0, /* Interrupt Mask Register */
55 VMXNET3_REG_TXPROD = 0x600, /* Tx Producer Index */
56 VMXNET3_REG_RXPROD = 0x800, /* Rx Producer Index for ring 1 */
57 VMXNET3_REG_RXPROD2 = 0xA00 /* Rx Producer Index for ring 2 */
62 VMXNET3_REG_LB_TXPROD = 0x1000, /* Tx Producer Index */
63 VMXNET3_REG_LB_RXPROD = 0x1400, /* Rx Producer Index for ring 1 */
64 VMXNET3_REG_LB_RXPROD2 = 0x1800, /* Rx Producer Index for ring 2 */
67 #define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */
70 #define VMXNET3_LARGE_BAR0_REG_SIZE (4096 * 4096) /* LARGE BAR 0 */
74 #define VMXNET3_REG_ALIGN_MASK 0x7
77 #define VMXNET3_IO_TYPE_PT 0
79 #define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF))
81 #define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF)
83 #define VMXNET3_PMC_PSEUDO_TSC 0x10003
86 VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
108 VMXNET3_CMD_FIRST_GET = 0xF00D0000,
134 * Byte 0 : 7.....len.....0
136 * Byte 2 : 5.msscof.0 ext1 dtype
140 * Byte 0: 13...msscof...6
141 * Byte 1 : 5.msscof.0 ext1 dtype
143 * Byte 3 : 7.....len.....0
189 #define VMXNET3_OM_NONE 0
216 #define VMXNET3_TCD_TXIDX_SHIFT 0
252 #define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */
287 u32 ext1:2; /* bit 0: indicating v4/v6/.. is for inner header */
292 u32 ext1:2; /* bit 0: indicating v4/v6/.. is for inner header */
393 #define VMXNET3_RCD_RSS_TYPE_NONE 0
432 /* Minimum size of a type 0 buffer */
477 VMXNET3_ERR_NOEOP = 0x80000000, /* cannot find the EOP desc of a pkt */
478 VMXNET3_ERR_TXD_REUSE = 0x80000001, /* reuse TxDesc before tx completion */
479 VMXNET3_ERR_BIG_PKT = 0x80000002, /* too many TxDesc for a pkt */
480 VMXNET3_ERR_DESC_NOT_SPT = 0x80000003, /* descriptor type not supported */
481 VMXNET3_ERR_SMALL_BUF = 0x80000004, /* type 0 buffer too small */
482 VMXNET3_ERR_STRESS = 0x80000005, /* stress option firing in vmkernel */
483 VMXNET3_ERR_SWITCH = 0x80000006, /* mode switch failure */
484 VMXNET3_ERR_TXD_INVALID = 0x80000007, /* invalid TxDesc */
488 #define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */
493 VMXNET3_GOS_BITS_UNK = 0, /* unknown */
600 VMXNET3_IMM_AUTO = 0,
606 VMXNET3_IT_AUTO = 0,
625 #define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */
676 VMXNET3_RXM_UCAST = 0x01, /* unicast only */
677 VMXNET3_RXM_MCAST = 0x02, /* multicast passing the filters */
678 VMXNET3_RXM_BCAST = 0x04, /* broadcast only */
679 VMXNET3_RXM_ALL_MULTI = 0x08, /* all multicast */
680 VMXNET3_RXM_PROMISC = 0x10 /* promiscuous */
696 #define VMXNET3_PM_WAKEUP_MAGIC cpu_to_le16(0x01) /* wake up on magic pkts */
697 #define VMXNET3_PM_WAKEUP_FILTER cpu_to_le16(0x02) /* wake up on pkts matching
756 VMXNET3_COALESCE_DISABLED = 0,
797 VMXNET3_RSS_FIELDS_TCPIP4 = 0x0001,
798 VMXNET3_RSS_FIELDS_TCPIP6 = 0x0002,
799 VMXNET3_RSS_FIELDS_UDPIP4 = 0x0004,
800 VMXNET3_RSS_FIELDS_UDPIP6 = 0x0008,
801 VMXNET3_RSS_FIELDS_ESPIP4 = 0x0010,
802 VMXNET3_RSS_FIELDS_ESPIP6 = 0x0020,
857 #define VMXNET3_ECR_RQERR (1 << 0)
864 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)
871 (idx) = 0;\
873 } while (0)
881 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
888 #define VMXNET3_LINK_DOWN 0
891 #define VMXNET3_CAP_UDP_RSS 0 /* bit 0 of DCR 0 */
892 #define VMXNET3_CAP_ESP_RSS_IPV4 1 /* bit 1 of DCR 0 */
893 #define VMXNET3_CAP_GENEVE_CHECKSUM_OFFLOAD 2 /* bit 2 of DCR 0 */
894 #define VMXNET3_CAP_GENEVE_TSO 3 /* bit 3 of DCR 0 */
895 #define VMXNET3_CAP_VXLAN_CHECKSUM_OFFLOAD 4 /* bit 4 of DCR 0 */
896 #define VMXNET3_CAP_VXLAN_TSO 5 /* bit 5 of DCR 0 */
897 #define VMXNET3_CAP_GENEVE_OUTER_CHECKSUM_OFFLOAD 6 /* bit 6 of DCR 0 */
898 #define VMXNET3_CAP_VXLAN_OUTER_CHECKSUM_OFFLOAD 7 /* bit 7 of DCR 0 */
899 #define VMXNET3_CAP_PKT_STEERING_IPV4 8 /* bit 8 of DCR 0 */
901 #define VMXNET3_CAP_ESP_RSS_IPV6 9 /* bit 9 of DCR 0 */
903 #define VMXNET3_CAP_ESP_OVER_UDP_RSS 10 /* bit 10 of DCR 0 */
904 #define VMXNET3_CAP_INNER_RSS 11 /* bit 11 of DCR 0 */
905 #define VMXNET3_CAP_INNER_ESP_RSS 12 /* bit 12 of DCR 0 */
906 #define VMXNET3_CAP_CRC32_HASH_FUNC 13 /* bit 13 of DCR 0 */
908 #define VMXNET3_CAP_OAM_FILTER 14 /* bit 14 of DCR 0 */
909 #define VMXNET3_CAP_ESP_QS 15 /* bit 15 of DCR 0 */
910 #define VMXNET3_CAP_LARGE_BAR 16 /* bit 16 of DCR 0 */
911 #define VMXNET3_CAP_OOORX_COMP 17 /* bit 17 of DCR 0 */
916 #define VMXNET3_OFFLOAD_TSO BIT(0)