Lines Matching +full:fifo +full:- +full:watermark +full:- +full:aligned
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2007-2008 SMSC
38 /* SCSRs - System Control and Status Registers */
57 #define INT_STS_TDFU_ (0x00002000) /* TX Data FIFO Underrun */
58 #define INT_STS_TDFO_ (0x00001000) /* TX Data FIFO Overrun */
65 #define RX_FIFO_FLUSH_ (0x00000001) /* Receive FIFO Flush */
71 #define TX_CFG_FIFO_FLUSH_ (0x00000001) /* Transmit FIFO Flush */
88 /* Receive FIFO Information Register */
90 #define RX_FIFO_INF_USED_ (0x0000FFFF) /* RX Data FIFO Used Space */
92 /* Transmit FIFO Information Register */
94 #define TX_FIFO_INF_FREE_ (0x0000FFFF) /* TX Data FIFO Free Space */
133 /* Hi watermark = 15.5Kb (~10 mtu pkts) */
134 /* low watermark = 3k (~2 mtu pkts) */
153 #define E2P_CMD_ADDR_ (0x000001FF) /* Byte aligned address */
167 #define STRAP_STATUS_PWR_SEL_ (0x00000020) /* Device self-powered */
168 #define STRAP_STATUS_AMDIX_EN_ (0x00000010) /* Auto-MDIX Enabled */
169 #define STRAP_STATUS_PORT_SWAP_ (0x00000008) /* USBD+/USBD- Swapped */
196 #define INT_EP_CTL_RX_FIFO_ (0x00040000) /* RX FIFO Has Frame */
201 #define INT_EP_CTL_TDFU_ (0x00002000) /* TX Data FIFO Underrun */
202 #define INT_EP_CTL_TDFO_ (0x00001000) /* TX Data FIFO Overrun */
209 /* MAC CSRs - MAC Control and Status Registers */
285 /* Vendor-specific PHY Definitions (via MII access) */
348 #define INT_ENP_TDFU_ ((u32)BIT(13)) /* TX FIFO Underrun */
349 #define INT_ENP_TDFO_ ((u32)BIT(12)) /* TX FIFO Overrun */