Lines Matching +full:0 +full:xfffffff0
19 #define INTERNAL_EPHY_ID 0x1234d400
37 #define TSTMODE_ENABLE 0x400
38 #define TSTMODE_DISABLE 0x0
40 #define WR_ADDR_A7CFG 0x18
74 * the default value is 0x8. in rockchip_integrated_phy_analog_init()
76 ret = phy_write(phydev, SMI_ADDR_TSTWRITE, 0xB); in rockchip_integrated_phy_analog_init()
95 if (val < 0) in rockchip_integrated_phy_config_init()
127 if (reg < 0) in rockchip_set_polarity()
142 return 0; in rockchip_set_polarity()
152 return 0; in rockchip_set_polarity()
160 if (err < 0) in rockchip_config_aneg()
176 .phy_id_mask = 0xfffffff0,
179 .flags = 0,
192 { INTERNAL_EPHY_ID, 0xfffffff0 },