Lines Matching full:phydev
287 void (*counters_enable)(struct phy_device *phydev);
291 void (*ptp_init)(struct phy_device *phydev);
292 void (*ptp_enable)(struct phy_device *phydev, bool enable);
293 void (*nmi_handler)(struct phy_device *phydev,
298 struct nxp_c45_phy_data *nxp_c45_get_data(struct phy_device *phydev) in nxp_c45_get_data() argument
300 return phydev->drv->driver_data; in nxp_c45_get_data()
304 struct nxp_c45_regmap *nxp_c45_get_regmap(struct phy_device *phydev) in nxp_c45_get_regmap() argument
306 const struct nxp_c45_phy_data *phy_data = nxp_c45_get_data(phydev); in nxp_c45_get_regmap()
311 static int nxp_c45_read_reg_field(struct phy_device *phydev, in nxp_c45_read_reg_field() argument
318 phydev_err(phydev, "Trying to read a reg field of size 0.\n"); in nxp_c45_read_reg_field()
322 ret = phy_read_mmd(phydev, reg_field->devad, reg_field->reg); in nxp_c45_read_reg_field()
335 static int nxp_c45_write_reg_field(struct phy_device *phydev, in nxp_c45_write_reg_field() argument
343 phydev_err(phydev, "Trying to write a reg field of size 0.\n"); in nxp_c45_write_reg_field()
352 return phy_modify_mmd_changed(phydev, reg_field->devad, in nxp_c45_write_reg_field()
356 static int nxp_c45_set_reg_field(struct phy_device *phydev, in nxp_c45_set_reg_field() argument
360 phydev_err(phydev, "Trying to set a reg field of size different than 1.\n"); in nxp_c45_set_reg_field()
364 return nxp_c45_write_reg_field(phydev, reg_field, 1); in nxp_c45_set_reg_field()
367 static int nxp_c45_clear_reg_field(struct phy_device *phydev, in nxp_c45_clear_reg_field() argument
371 phydev_err(phydev, "Trying to set a reg field of size different than 1.\n"); in nxp_c45_clear_reg_field()
375 return nxp_c45_write_reg_field(phydev, reg_field, 0); in nxp_c45_clear_reg_field()
378 static bool nxp_c45_poll_txts(struct phy_device *phydev) in nxp_c45_poll_txts() argument
380 return phydev->irq <= 0; in nxp_c45_poll_txts()
388 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev); in _nxp_c45_ptp_gettimex64()
390 nxp_c45_set_reg_field(priv->phydev, ®map->ltc_read); in _nxp_c45_ptp_gettimex64()
391 ts->tv_nsec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
393 ts->tv_nsec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
395 ts->tv_sec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
397 ts->tv_sec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
420 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev); in _nxp_c45_ptp_settime64()
422 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_0, in _nxp_c45_ptp_settime64()
424 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_1, in _nxp_c45_ptp_settime64()
426 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_0, in _nxp_c45_ptp_settime64()
428 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_1, in _nxp_c45_ptp_settime64()
430 nxp_c45_set_reg_field(priv->phydev, ®map->ltc_write); in _nxp_c45_ptp_settime64()
450 const struct nxp_c45_phy_data *data = nxp_c45_get_data(priv->phydev); in nxp_c45_ptp_adjfine()
462 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_adjfine()
470 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_adjfine()
515 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev); in nxp_c45_get_extts()
517 extts->tv_nsec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
519 extts->tv_nsec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
521 extts->tv_sec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
523 extts->tv_sec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
525 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
531 static bool tja1120_extts_is_valid(struct phy_device *phydev) in tja1120_extts_is_valid() argument
536 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, in tja1120_extts_is_valid()
546 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev); in tja1120_get_extts()
547 struct phy_device *phydev = priv->phydev; in tja1120_get_extts() local
552 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, in tja1120_get_extts()
556 valid = tja1120_extts_is_valid(phydev); in tja1120_get_extts()
564 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1120_get_extts()
566 valid = tja1120_extts_is_valid(phydev); in tja1120_get_extts()
579 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev); in nxp_c45_read_egress_ts()
580 struct phy_device *phydev = priv->phydev; in nxp_c45_read_egress_ts() local
583 nxp_c45_read_reg_field(phydev, ®map->domain_number); in nxp_c45_read_egress_ts()
585 nxp_c45_read_reg_field(phydev, ®map->msg_type); in nxp_c45_read_egress_ts()
587 nxp_c45_read_reg_field(phydev, ®map->sequence_id); in nxp_c45_read_egress_ts()
589 nxp_c45_read_reg_field(phydev, ®map->nsec_15_0); in nxp_c45_read_egress_ts()
591 nxp_c45_read_reg_field(phydev, ®map->nsec_29_16) << 16; in nxp_c45_read_egress_ts()
592 hwts->sec = nxp_c45_read_reg_field(phydev, ®map->sec_1_0); in nxp_c45_read_egress_ts()
593 hwts->sec |= nxp_c45_read_reg_field(phydev, ®map->sec_4_2) << 2; in nxp_c45_read_egress_ts()
603 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_CTRL, in nxp_c45_get_hwtxts()
605 reg = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_DATA_0); in nxp_c45_get_hwtxts()
616 static bool tja1120_egress_ts_is_valid(struct phy_device *phydev) in tja1120_egress_ts_is_valid() argument
621 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_DATA_S); in tja1120_egress_ts_is_valid()
630 struct phy_device *phydev = priv->phydev; in tja1120_get_hwtxts() local
636 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_END); in tja1120_get_hwtxts()
638 valid = tja1120_egress_ts_is_valid(phydev); in tja1120_get_hwtxts()
646 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1120_get_hwtxts()
648 valid = tja1120_egress_ts_is_valid(phydev); in tja1120_get_hwtxts()
653 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_DATA_S, in tja1120_get_hwtxts()
690 phydev_warn(priv->phydev, in nxp_c45_process_txts()
698 const struct nxp_c45_phy_data *data = nxp_c45_get_data(priv->phydev); in nxp_c45_do_aux_work()
699 bool poll_txts = nxp_c45_poll_txts(priv->phydev); in nxp_c45_do_aux_work()
750 struct phy_device *phydev = priv->phydev; in nxp_c45_gpio_config() local
752 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_gpio_config()
759 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev); in nxp_c45_perout_enable()
760 struct phy_device *phydev = priv->phydev; in nxp_c45_perout_enable() local
771 nxp_c45_clear_reg_field(priv->phydev, in nxp_c45_perout_enable()
773 nxp_c45_clear_reg_field(priv->phydev, in nxp_c45_perout_enable()
786 phydev_warn(phydev, "The period can be set only to 1 second."); in nxp_c45_perout_enable()
792 …phydev_warn(phydev, "The start time is not configurable. Should be set to 0 seconds and 0 nanoseco… in nxp_c45_perout_enable()
798 phydev_warn(phydev, "The phase can be set only to 0 or 500000000 nanoseconds."); in nxp_c45_perout_enable()
803 nxp_c45_clear_reg_field(priv->phydev, in nxp_c45_perout_enable()
806 nxp_c45_set_reg_field(priv->phydev, in nxp_c45_perout_enable()
812 nxp_c45_set_reg_field(priv->phydev, ®map->pps_enable); in nxp_c45_perout_enable()
817 static void nxp_c45_set_rising_or_falling(struct phy_device *phydev, in nxp_c45_set_rising_or_falling() argument
821 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_or_falling()
825 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_or_falling()
829 static void nxp_c45_set_rising_and_falling(struct phy_device *phydev, in nxp_c45_set_rising_and_falling() argument
837 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_and_falling()
841 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_and_falling()
846 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_and_falling()
850 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_and_falling()
858 const struct nxp_c45_phy_data *data = nxp_c45_get_data(priv->phydev); in nxp_c45_extts_enable()
885 nxp_c45_set_rising_and_falling(priv->phydev, extts); in nxp_c45_extts_enable()
887 nxp_c45_set_rising_or_falling(priv->phydev, extts); in nxp_c45_extts_enable()
965 &priv->phydev->mdio.dev); in nxp_c45_init_ptp_clock()
988 if (nxp_c45_poll_txts(priv->phydev)) in nxp_c45_txtstamp()
1024 struct phy_device *phydev = priv->phydev; in nxp_c45_hwtstamp() local
1030 data = nxp_c45_get_data(phydev); in nxp_c45_hwtstamp()
1048 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_hwtstamp()
1051 data->ptp_enable(phydev, true); in nxp_c45_hwtstamp()
1053 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_hwtstamp()
1056 data->ptp_enable(phydev, false); in nxp_c45_hwtstamp()
1059 if (nxp_c45_poll_txts(priv->phydev)) in nxp_c45_hwtstamp()
1063 nxp_c45_set_reg_field(phydev, &data->regmap->irq_egr_ts_en); in nxp_c45_hwtstamp()
1065 nxp_c45_clear_reg_field(phydev, &data->regmap->irq_egr_ts_en); in nxp_c45_hwtstamp()
1135 static int nxp_c45_get_sset_count(struct phy_device *phydev) in nxp_c45_get_sset_count() argument
1137 const struct nxp_c45_phy_data *phy_data = nxp_c45_get_data(phydev); in nxp_c45_get_sset_count()
1142 static void nxp_c45_get_strings(struct phy_device *phydev, u8 *data) in nxp_c45_get_strings() argument
1144 const struct nxp_c45_phy_data *phy_data = nxp_c45_get_data(phydev); in nxp_c45_get_strings()
1145 size_t count = nxp_c45_get_sset_count(phydev); in nxp_c45_get_strings()
1159 static void nxp_c45_get_stats(struct phy_device *phydev, in nxp_c45_get_stats() argument
1162 const struct nxp_c45_phy_data *phy_data = nxp_c45_get_data(phydev); in nxp_c45_get_stats()
1163 size_t count = nxp_c45_get_sset_count(phydev); in nxp_c45_get_stats()
1177 ret = nxp_c45_read_reg_field(phydev, reg_field); in nxp_c45_get_stats()
1185 static int nxp_c45_config_enable(struct phy_device *phydev) in nxp_c45_config_enable() argument
1187 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, in nxp_c45_config_enable()
1192 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_CONTROL, in nxp_c45_config_enable()
1194 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL, in nxp_c45_config_enable()
1196 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_INFRA_CONTROL, in nxp_c45_config_enable()
1202 static int nxp_c45_start_op(struct phy_device *phydev) in nxp_c45_start_op() argument
1204 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL, in nxp_c45_start_op()
1208 static int nxp_c45_config_intr(struct phy_device *phydev) in nxp_c45_config_intr() argument
1212 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in nxp_c45_config_intr()
1213 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_config_intr()
1218 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_config_intr()
1222 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_config_intr()
1227 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_config_intr()
1231 static int tja1103_config_intr(struct phy_device *phydev) in tja1103_config_intr() argument
1236 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_ALWAYS_ACCESSIBLE, in tja1103_config_intr()
1241 return nxp_c45_config_intr(phydev); in tja1103_config_intr()
1244 static int tja1120_config_intr(struct phy_device *phydev) in tja1120_config_intr() argument
1248 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in tja1120_config_intr()
1249 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_config_intr()
1253 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_config_intr()
1259 return nxp_c45_config_intr(phydev); in tja1120_config_intr()
1262 static irqreturn_t nxp_c45_handle_interrupt(struct phy_device *phydev) in nxp_c45_handle_interrupt() argument
1264 const struct nxp_c45_phy_data *data = nxp_c45_get_data(phydev); in nxp_c45_handle_interrupt()
1265 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_handle_interrupt()
1270 irq = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_IRQ_STATUS); in nxp_c45_handle_interrupt()
1272 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_IRQ_ACK, in nxp_c45_handle_interrupt()
1274 phy_trigger_machine(phydev); in nxp_c45_handle_interrupt()
1278 irq = nxp_c45_read_reg_field(phydev, &data->regmap->irq_egr_ts_status); in nxp_c45_handle_interrupt()
1285 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_handle_interrupt()
1293 data->nmi_handler(phydev, &ret); in nxp_c45_handle_interrupt()
1294 nxp_c45_handle_macsec_interrupt(phydev, &ret); in nxp_c45_handle_interrupt()
1299 static int nxp_c45_soft_reset(struct phy_device *phydev) in nxp_c45_soft_reset() argument
1303 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, in nxp_c45_soft_reset()
1310 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, in nxp_c45_soft_reset()
1316 static int nxp_c45_cable_test_start(struct phy_device *phydev) in nxp_c45_cable_test_start() argument
1318 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(phydev); in nxp_c45_cable_test_start()
1320 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_cable_test_start()
1322 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test, in nxp_c45_cable_test_start()
1326 static int nxp_c45_cable_test_get_status(struct phy_device *phydev, in nxp_c45_cable_test_get_status() argument
1329 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(phydev); in nxp_c45_cable_test_get_status()
1333 ret = nxp_c45_read_reg_field(phydev, ®map->cable_test_valid); in nxp_c45_cable_test_get_status()
1340 cable_test_result = nxp_c45_read_reg_field(phydev, in nxp_c45_cable_test_get_status()
1345 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, in nxp_c45_cable_test_get_status()
1349 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, in nxp_c45_cable_test_get_status()
1353 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, in nxp_c45_cable_test_get_status()
1357 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, in nxp_c45_cable_test_get_status()
1361 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test, in nxp_c45_cable_test_get_status()
1363 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_cable_test_get_status()
1366 return nxp_c45_start_op(phydev); in nxp_c45_cable_test_get_status()
1369 static int nxp_c45_get_sqi(struct phy_device *phydev) in nxp_c45_get_sqi() argument
1373 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_SIGNAL_QUALITY); in nxp_c45_get_sqi()
1382 static void tja1120_link_change_notify(struct phy_device *phydev) in tja1120_link_change_notify() argument
1387 if (phydev->state == PHY_NOLINK) { in tja1120_link_change_notify()
1388 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_link_change_notify()
1390 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_link_change_notify()
1395 static int nxp_c45_get_sqi_max(struct phy_device *phydev) in nxp_c45_get_sqi_max() argument
1400 static int nxp_c45_check_delay(struct phy_device *phydev, u32 delay) in nxp_c45_check_delay() argument
1403 phydev_err(phydev, "delay value smaller than %u\n", MIN_ID_PS); in nxp_c45_check_delay()
1408 phydev_err(phydev, "delay value higher than %u\n", MAX_ID_PS); in nxp_c45_check_delay()
1415 static void nxp_c45_counters_enable(struct phy_device *phydev) in nxp_c45_counters_enable() argument
1417 const struct nxp_c45_phy_data *data = nxp_c45_get_data(phydev); in nxp_c45_counters_enable()
1419 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_LINK_DROP_COUNTER, in nxp_c45_counters_enable()
1422 data->counters_enable(phydev); in nxp_c45_counters_enable()
1425 static void nxp_c45_ptp_init(struct phy_device *phydev) in nxp_c45_ptp_init() argument
1427 const struct nxp_c45_phy_data *data = nxp_c45_get_data(phydev); in nxp_c45_ptp_init()
1429 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_init()
1432 nxp_c45_clear_reg_field(phydev, &data->regmap->ltc_lock_ctrl); in nxp_c45_ptp_init()
1434 data->ptp_init(phydev); in nxp_c45_ptp_init()
1448 static void nxp_c45_disable_delays(struct phy_device *phydev) in nxp_c45_disable_delays() argument
1450 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, ID_ENABLE); in nxp_c45_disable_delays()
1451 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, ID_ENABLE); in nxp_c45_disable_delays()
1454 static void nxp_c45_set_delays(struct phy_device *phydev) in nxp_c45_set_delays() argument
1456 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_set_delays()
1461 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in nxp_c45_set_delays()
1462 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { in nxp_c45_set_delays()
1464 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, in nxp_c45_set_delays()
1467 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, in nxp_c45_set_delays()
1471 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in nxp_c45_set_delays()
1472 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { in nxp_c45_set_delays()
1474 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, in nxp_c45_set_delays()
1477 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, in nxp_c45_set_delays()
1482 static int nxp_c45_get_delays(struct phy_device *phydev) in nxp_c45_get_delays() argument
1484 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_get_delays()
1487 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in nxp_c45_get_delays()
1488 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { in nxp_c45_get_delays()
1489 ret = device_property_read_u32(&phydev->mdio.dev, in nxp_c45_get_delays()
1495 ret = nxp_c45_check_delay(phydev, priv->tx_delay); in nxp_c45_get_delays()
1497 phydev_err(phydev, in nxp_c45_get_delays()
1503 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in nxp_c45_get_delays()
1504 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { in nxp_c45_get_delays()
1505 ret = device_property_read_u32(&phydev->mdio.dev, in nxp_c45_get_delays()
1511 ret = nxp_c45_check_delay(phydev, priv->rx_delay); in nxp_c45_get_delays()
1513 phydev_err(phydev, in nxp_c45_get_delays()
1522 static int nxp_c45_set_phy_mode(struct phy_device *phydev) in nxp_c45_set_phy_mode() argument
1524 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_set_phy_mode()
1528 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_ABILITIES); in nxp_c45_set_phy_mode()
1529 phydev_dbg(phydev, "Clause 45 managed PHY abilities 0x%x\n", ret); in nxp_c45_set_phy_mode()
1531 switch (phydev->interface) { in nxp_c45_set_phy_mode()
1534 phydev_err(phydev, "rgmii mode not supported\n"); in nxp_c45_set_phy_mode()
1537 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1539 nxp_c45_disable_delays(phydev); in nxp_c45_set_phy_mode()
1545 phydev_err(phydev, "rgmii-id, rgmii-txid, rgmii-rxid modes are not supported\n"); in nxp_c45_set_phy_mode()
1548 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1550 ret = nxp_c45_get_delays(phydev); in nxp_c45_set_phy_mode()
1554 nxp_c45_set_delays(phydev); in nxp_c45_set_phy_mode()
1558 phydev_err(phydev, "mii mode not supported\n"); in nxp_c45_set_phy_mode()
1561 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1566 phydev_err(phydev, "rev-mii mode not supported\n"); in nxp_c45_set_phy_mode()
1569 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1574 phydev_err(phydev, "rmii mode not supported\n"); in nxp_c45_set_phy_mode()
1584 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1589 phydev_err(phydev, "sgmii mode not supported\n"); in nxp_c45_set_phy_mode()
1592 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1605 static void nxp_c45_tja1120_errata(struct phy_device *phydev) in nxp_c45_tja1120_errata() argument
1612 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_ID3); in nxp_c45_tja1120_errata()
1622 phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_tja1120_errata()
1632 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x4b95); in nxp_c45_tja1120_errata()
1633 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0xf3cd); in nxp_c45_tja1120_errata()
1635 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x89c7); in nxp_c45_tja1120_errata()
1636 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0893); in nxp_c45_tja1120_errata()
1639 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0476, 0x58a0); in nxp_c45_tja1120_errata()
1641 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x8921, 0xa3a); in nxp_c45_tja1120_errata()
1642 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x89F1, 0x16c1); in nxp_c45_tja1120_errata()
1644 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x0); in nxp_c45_tja1120_errata()
1645 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0); in nxp_c45_tja1120_errata()
1651 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_tja1120_errata()
1654 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_tja1120_errata()
1661 static int nxp_c45_config_init(struct phy_device *phydev) in nxp_c45_config_init() argument
1665 ret = nxp_c45_config_enable(phydev); in nxp_c45_config_init()
1667 phydev_err(phydev, "Failed to enable config\n"); in nxp_c45_config_init()
1674 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 1); in nxp_c45_config_init()
1675 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 2); in nxp_c45_config_init()
1677 if (phy_id_compare(phydev->phy_id, PHY_ID_TJA_1120, GENMASK(31, 4))) in nxp_c45_config_init()
1678 nxp_c45_tja1120_errata(phydev); in nxp_c45_config_init()
1680 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONFIG, in nxp_c45_config_init()
1683 ret = nxp_c45_set_phy_mode(phydev); in nxp_c45_config_init()
1687 phydev->autoneg = AUTONEG_DISABLE; in nxp_c45_config_init()
1689 nxp_c45_counters_enable(phydev); in nxp_c45_config_init()
1690 nxp_c45_ptp_init(phydev); in nxp_c45_config_init()
1691 ret = nxp_c45_macsec_config_init(phydev); in nxp_c45_config_init()
1695 return nxp_c45_start_op(phydev); in nxp_c45_config_init()
1698 static int nxp_c45_get_features(struct phy_device *phydev) in nxp_c45_get_features() argument
1700 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported); in nxp_c45_get_features()
1701 linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, phydev->supported); in nxp_c45_get_features()
1703 return genphy_c45_pma_read_abilities(phydev); in nxp_c45_get_features()
1706 static int nxp_c45_parse_dt(struct phy_device *phydev) in nxp_c45_parse_dt() argument
1708 struct device_node *node = phydev->mdio.dev.of_node; in nxp_c45_parse_dt()
1709 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_parse_dt()
1720 static int nxp_c45_probe(struct phy_device *phydev) in nxp_c45_probe() argument
1728 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); in nxp_c45_probe()
1735 priv->phydev = phydev; in nxp_c45_probe()
1737 phydev->priv = priv; in nxp_c45_probe()
1739 nxp_c45_parse_dt(phydev); in nxp_c45_probe()
1743 phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_probe()
1747 phydev_dbg(phydev, "the phy does not support PTP"); in nxp_c45_probe()
1757 phydev->mii_ts = &priv->mii_ts; in nxp_c45_probe()
1761 phydev->default_timestamp = true; in nxp_c45_probe()
1763 phydev_dbg(phydev, "PTP support not enabled even if the phy supports it"); in nxp_c45_probe()
1769 phydev_info(phydev, "the phy does not support MACsec\n"); in nxp_c45_probe()
1774 ret = nxp_c45_macsec_probe(phydev); in nxp_c45_probe()
1775 phydev_dbg(phydev, "MACsec support enabled."); in nxp_c45_probe()
1777 phydev_dbg(phydev, "MACsec support not enabled even if the phy supports it"); in nxp_c45_probe()
1785 static void nxp_c45_remove(struct phy_device *phydev) in nxp_c45_remove() argument
1787 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_remove()
1794 nxp_c45_macsec_remove(phydev); in nxp_c45_remove()
1797 static void tja1103_counters_enable(struct phy_device *phydev) in tja1103_counters_enable() argument
1799 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_PREAMBLE_COUNT, in tja1103_counters_enable()
1801 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TX_PREAMBLE_COUNT, in tja1103_counters_enable()
1803 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_IPG_LENGTH, in tja1103_counters_enable()
1805 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TX_IPG_LENGTH, in tja1103_counters_enable()
1809 static void tja1103_ptp_init(struct phy_device *phydev) in tja1103_ptp_init() argument
1811 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_TS_INSRT_CTRL, in tja1103_ptp_init()
1813 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_FUNC_ENABLES, in tja1103_ptp_init()
1817 static void tja1103_ptp_enable(struct phy_device *phydev, bool enable) in tja1103_ptp_enable() argument
1820 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1103_ptp_enable()
1824 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1103_ptp_enable()
1829 static void tja1103_nmi_handler(struct phy_device *phydev, in tja1103_nmi_handler() argument
1834 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, in tja1103_nmi_handler()
1837 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1103_nmi_handler()
1912 static void tja1120_counters_enable(struct phy_device *phydev) in tja1120_counters_enable() argument
1914 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_SYMBOL_ERROR_CNT_XTD, in tja1120_counters_enable()
1916 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_MONITOR_STATUS, in tja1120_counters_enable()
1918 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_MONITOR_CONFIG, in tja1120_counters_enable()
1922 static void tja1120_ptp_init(struct phy_device *phydev) in tja1120_ptp_init() argument
1924 phy_write_mmd(phydev, MDIO_MMD_VEND1, TJA1120_RX_TS_INSRT_CTRL, in tja1120_ptp_init()
1926 phy_write_mmd(phydev, MDIO_MMD_VEND1, TJA1120_VEND1_EXT_TS_MODE, in tja1120_ptp_init()
1928 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONFIG, in tja1120_ptp_init()
1932 static void tja1120_ptp_enable(struct phy_device *phydev, bool enable) in tja1120_ptp_enable() argument
1935 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_ptp_enable()
1939 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_ptp_enable()
1944 static void tja1120_nmi_handler(struct phy_device *phydev, in tja1120_nmi_handler() argument
1949 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, in tja1120_nmi_handler()
1952 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1120_nmi_handler()