Lines Matching full:phydev
14 static int pll5g_detune(struct phy_device *phydev) in pll5g_detune() argument
19 rd_dat = vsc85xx_csr_read(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2); in pll5g_detune()
22 ret = vsc85xx_csr_write(phydev, MACRO_CTRL, in pll5g_detune()
25 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in pll5g_detune()
29 static int pll5g_tune(struct phy_device *phydev) in pll5g_tune() argument
34 rd_dat = vsc85xx_csr_read(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2); in pll5g_tune()
36 ret = vsc85xx_csr_write(phydev, MACRO_CTRL, in pll5g_tune()
39 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in pll5g_tune()
43 static int vsc85xx_sd6g_pll_cfg_wr(struct phy_device *phydev, in vsc85xx_sd6g_pll_cfg_wr() argument
50 ret = vsc85xx_csr_write(phydev, MACRO_CTRL, in vsc85xx_sd6g_pll_cfg_wr()
56 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_pll_cfg_wr()
60 static int vsc85xx_sd6g_common_cfg_wr(struct phy_device *phydev, in vsc85xx_sd6g_common_cfg_wr() argument
77 ret = vsc85xx_csr_write(phydev, MACRO_CTRL, in vsc85xx_sd6g_common_cfg_wr()
85 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_common_cfg_wr()
89 static int vsc85xx_sd6g_des_cfg_wr(struct phy_device *phydev, in vsc85xx_sd6g_des_cfg_wr() argument
105 ret = vsc85xx_csr_write(phydev, MACRO_CTRL, in vsc85xx_sd6g_des_cfg_wr()
109 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_des_cfg_wr()
113 static int vsc85xx_sd6g_ib_cfg0_wr(struct phy_device *phydev, in vsc85xx_sd6g_ib_cfg0_wr() argument
130 ret = vsc85xx_csr_write(phydev, MACRO_CTRL, in vsc85xx_sd6g_ib_cfg0_wr()
134 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_ib_cfg0_wr()
138 static int vsc85xx_sd6g_ib_cfg1_wr(struct phy_device *phydev, in vsc85xx_sd6g_ib_cfg1_wr() argument
154 ret = vsc85xx_csr_write(phydev, MACRO_CTRL, in vsc85xx_sd6g_ib_cfg1_wr()
158 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_ib_cfg1_wr()
162 static int vsc85xx_sd6g_ib_cfg2_wr(struct phy_device *phydev, in vsc85xx_sd6g_ib_cfg2_wr() argument
176 ret = vsc85xx_csr_write(phydev, MACRO_CTRL, in vsc85xx_sd6g_ib_cfg2_wr()
180 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_ib_cfg2_wr()
184 static int vsc85xx_sd6g_ib_cfg3_wr(struct phy_device *phydev, in vsc85xx_sd6g_ib_cfg3_wr() argument
195 ret = vsc85xx_csr_write(phydev, MACRO_CTRL, in vsc85xx_sd6g_ib_cfg3_wr()
199 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_ib_cfg3_wr()
203 static int vsc85xx_sd6g_ib_cfg4_wr(struct phy_device *phydev, in vsc85xx_sd6g_ib_cfg4_wr() argument
214 ret = vsc85xx_csr_write(phydev, MACRO_CTRL, in vsc85xx_sd6g_ib_cfg4_wr()
218 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_ib_cfg4_wr()
222 static int vsc85xx_sd6g_misc_cfg_wr(struct phy_device *phydev, in vsc85xx_sd6g_misc_cfg_wr() argument
227 ret = vsc85xx_csr_write(phydev, MACRO_CTRL, in vsc85xx_sd6g_misc_cfg_wr()
231 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_misc_cfg_wr()
235 static int vsc85xx_sd6g_gp_cfg_wr(struct phy_device *phydev, const u32 gp_cfg_val) in vsc85xx_sd6g_gp_cfg_wr() argument
239 ret = vsc85xx_csr_write(phydev, MACRO_CTRL, in vsc85xx_sd6g_gp_cfg_wr()
243 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_gp_cfg_wr()
247 static int vsc85xx_sd6g_dft_cfg2_wr(struct phy_device *phydev, in vsc85xx_sd6g_dft_cfg2_wr() argument
262 ret = vsc85xx_csr_write(phydev, MACRO_CTRL, in vsc85xx_sd6g_dft_cfg2_wr()
266 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_dft_cfg2_wr()
270 static int vsc85xx_sd6g_dft_cfg0_wr(struct phy_device *phydev, in vsc85xx_sd6g_dft_cfg0_wr() argument
280 ret = vsc85xx_csr_write(phydev, MACRO_CTRL, in vsc85xx_sd6g_dft_cfg0_wr()
284 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_dft_cfg0_wr()
289 static int vsc85xx_pll5g_cfg0_wr(struct phy_device *phydev, in vsc85xx_pll5g_cfg0_wr() argument
300 ret = vsc85xx_csr_write(phydev, MACRO_CTRL, in vsc85xx_pll5g_cfg0_wr()
303 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_pll5g_cfg0_wr()
307 int vsc85xx_sd6g_config_v2(struct phy_device *phydev) in vsc85xx_sd6g_config_v2() argument
325 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc85xx_sd6g_config_v2()
328 ret = pll5g_detune(phydev); in vsc85xx_sd6g_config_v2()
333 ret = vsc85xx_sd6g_pll_cfg_wr(phydev, 3, pll_fsm_ctrl_data, 0); in vsc85xx_sd6g_config_v2()
336 ret = vsc85xx_sd6g_common_cfg_wr(phydev, 0, 0, 0, qrate, if_mode, 0); in vsc85xx_sd6g_config_v2()
339 ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc85xx_sd6g_config_v2()
342 ret = vsc85xx_sd6g_des_cfg_wr(phydev, 6, 2, 5, des_bw_ana_val, 0); in vsc85xx_sd6g_config_v2()
348 ret = vsc85xx_sd6g_ib_cfg0_wr(phydev, ib_rtrm_adj, ib_sig_det_clk_sel_mm, 0, 0); in vsc85xx_sd6g_config_v2()
351 ret = vsc85xx_sd6g_ib_cfg1_wr(phydev, 8, ib_tsdet_mm, 15, 0, 1); in vsc85xx_sd6g_config_v2()
354 ret = vsc85xx_sd6g_ib_cfg2_wr(phydev, 3, 13, 5); in vsc85xx_sd6g_config_v2()
357 ret = vsc85xx_sd6g_ib_cfg3_wr(phydev, 0, 31, 1, 31); in vsc85xx_sd6g_config_v2()
360 ret = vsc85xx_sd6g_ib_cfg4_wr(phydev, 63, 63, 2, 63); in vsc85xx_sd6g_config_v2()
363 ret = vsc85xx_sd6g_common_cfg_wr(phydev, 1, 1, 0, qrate, if_mode, 0); in vsc85xx_sd6g_config_v2()
366 ret = vsc85xx_sd6g_misc_cfg_wr(phydev, 1); in vsc85xx_sd6g_config_v2()
369 ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc85xx_sd6g_config_v2()
374 ret = vsc85xx_sd6g_pll_cfg_wr(phydev, 3, pll_fsm_ctrl_data, 1); in vsc85xx_sd6g_config_v2()
377 ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc85xx_sd6g_config_v2()
384 ret = phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc85xx_sd6g_config_v2()
387 val32 = vsc85xx_csr_read(phydev, MACRO_CTRL, in vsc85xx_sd6g_config_v2()
396 ret = vsc85xx_sd6g_misc_cfg_wr(phydev, 0); in vsc85xx_sd6g_config_v2()
399 ret = vsc85xx_sd6g_common_cfg_wr(phydev, 1, 1, 0, qrate, if_mode, 1); in vsc85xx_sd6g_config_v2()
402 ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc85xx_sd6g_config_v2()
407 ret = vsc85xx_sd6g_gp_cfg_wr(phydev, 768); in vsc85xx_sd6g_config_v2()
410 ret = vsc85xx_sd6g_dft_cfg2_wr(phydev, 0, 2, 0, 0, 0, 1); in vsc85xx_sd6g_config_v2()
413 ret = vsc85xx_sd6g_dft_cfg0_wr(phydev, 0, 0, 1); in vsc85xx_sd6g_config_v2()
416 ret = vsc85xx_sd6g_des_cfg_wr(phydev, 6, 2, 5, des_bw_ana_val, 2); in vsc85xx_sd6g_config_v2()
419 ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc85xx_sd6g_config_v2()
424 ret = vsc85xx_sd6g_ib_cfg1_wr(phydev, 8, ib_tsdet_cal, 15, 1, 0); in vsc85xx_sd6g_config_v2()
427 ret = vsc85xx_sd6g_ib_cfg0_wr(phydev, ib_rtrm_adj, ib_sig_det_clk_sel_cal, 0, 0); in vsc85xx_sd6g_config_v2()
430 ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc85xx_sd6g_config_v2()
435 ret = vsc85xx_sd6g_ib_cfg0_wr(phydev, ib_rtrm_adj, in vsc85xx_sd6g_config_v2()
439 ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc85xx_sd6g_config_v2()
445 ret = vsc85xx_sd6g_gp_cfg_wr(phydev, 769); in vsc85xx_sd6g_config_v2()
448 ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc85xx_sd6g_config_v2()
452 ret = vsc85xx_sd6g_gp_cfg_wr(phydev, 768); in vsc85xx_sd6g_config_v2()
455 ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc85xx_sd6g_config_v2()
460 ret = vsc85xx_sd6g_ib_cfg1_wr(phydev, 8, ib_tsdet_cal, 15, 1, 1); in vsc85xx_sd6g_config_v2()
463 ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc85xx_sd6g_config_v2()
466 ret = vsc85xx_sd6g_ib_cfg1_wr(phydev, 8, ib_tsdet_cal, 15, 0, 1); in vsc85xx_sd6g_config_v2()
469 ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc85xx_sd6g_config_v2()
477 ret = phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc85xx_sd6g_config_v2()
480 val32 = vsc85xx_csr_read(phydev, MACRO_CTRL, in vsc85xx_sd6g_config_v2()
489 ret = vsc85xx_sd6g_ib_cfg0_wr(phydev, ib_rtrm_adj, ib_sig_det_clk_sel_mm, 0, 1); in vsc85xx_sd6g_config_v2()
492 ret = vsc85xx_sd6g_ib_cfg1_wr(phydev, 8, ib_tsdet_mm, 15, 0, 1); in vsc85xx_sd6g_config_v2()
495 ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc85xx_sd6g_config_v2()
500 ret = vsc85xx_sd6g_common_cfg_wr(phydev, 1, 1, 0, qrate, if_mode, 0); in vsc85xx_sd6g_config_v2()
503 ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc85xx_sd6g_config_v2()
508 ret = vsc85xx_sd6g_dft_cfg2_wr(phydev, 0, 0, 0, 0, 0, 0); in vsc85xx_sd6g_config_v2()
511 ret = vsc85xx_sd6g_dft_cfg0_wr(phydev, 0, 0, 0); in vsc85xx_sd6g_config_v2()
514 ret = vsc85xx_sd6g_des_cfg_wr(phydev, 6, 2, 5, des_bw_ana_val, 0); in vsc85xx_sd6g_config_v2()
517 ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc85xx_sd6g_config_v2()
522 ret = pll5g_tune(phydev); in vsc85xx_sd6g_config_v2()
528 ret = vsc85xx_sd6g_pll_cfg_wr(phydev, 3, pll_fsm_ctrl_data, 0); in vsc85xx_sd6g_config_v2()
531 ret = vsc85xx_sd6g_common_cfg_wr(phydev, 0, 1, 0, qrate, if_mode, 0); in vsc85xx_sd6g_config_v2()
534 ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc85xx_sd6g_config_v2()
539 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_GPIO); in vsc85xx_sd6g_config_v2()
540 ret = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); in vsc85xx_sd6g_config_v2()
550 ret = vsc8584_cmd(phydev, val); in vsc85xx_sd6g_config_v2()
552 dev_err(&phydev->mdio.dev, "%s: QSGMII error: %d\n", in vsc85xx_sd6g_config_v2()
557 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc85xx_sd6g_config_v2()
568 ret = vsc8584_cmd(phydev, val); in vsc85xx_sd6g_config_v2()
570 dev_err(&phydev->mdio.dev, "%s: SGMII error: %d\n", in vsc85xx_sd6g_config_v2()
575 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc85xx_sd6g_config_v2()
577 dev_err(&phydev->mdio.dev, "%s: invalid mac_if: %x\n", in vsc85xx_sd6g_config_v2()
581 ret = phy_update_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0); in vsc85xx_sd6g_config_v2()
584 ret = phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc85xx_sd6g_config_v2()
587 ret = vsc85xx_pll5g_cfg0_wr(phydev, 4); in vsc85xx_sd6g_config_v2()
590 ret = phy_commit_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0); in vsc85xx_sd6g_config_v2()
593 ret = vsc85xx_sd6g_des_cfg_wr(phydev, 6, 2, 5, des_bw_ana_val, 0); in vsc85xx_sd6g_config_v2()
596 ret = vsc85xx_sd6g_ib_cfg0_wr(phydev, ib_rtrm_adj, ib_sig_det_clk_sel_mm, 0, 1); in vsc85xx_sd6g_config_v2()
599 ret = vsc85xx_sd6g_ib_cfg1_wr(phydev, 8, ib_tsdet_mm, 15, 0, 1); in vsc85xx_sd6g_config_v2()
602 ret = vsc85xx_sd6g_common_cfg_wr(phydev, 1, 1, 0, qrate, if_mode, 0); in vsc85xx_sd6g_config_v2()
605 ret = vsc85xx_sd6g_ib_cfg2_wr(phydev, 3, 13, 5); in vsc85xx_sd6g_config_v2()
608 ret = vsc85xx_sd6g_ib_cfg3_wr(phydev, 0, 31, 1, 31); in vsc85xx_sd6g_config_v2()
611 ret = vsc85xx_sd6g_ib_cfg4_wr(phydev, 63, 63, 2, 63); in vsc85xx_sd6g_config_v2()
614 ret = vsc85xx_sd6g_misc_cfg_wr(phydev, 1); in vsc85xx_sd6g_config_v2()
617 ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc85xx_sd6g_config_v2()
622 ret = vsc85xx_sd6g_pll_cfg_wr(phydev, 3, pll_fsm_ctrl_data, 1); in vsc85xx_sd6g_config_v2()
625 ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc85xx_sd6g_config_v2()
633 ret = phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc85xx_sd6g_config_v2()
636 val32 = vsc85xx_csr_read(phydev, MACRO_CTRL, in vsc85xx_sd6g_config_v2()
645 ret = vsc85xx_sd6g_misc_cfg_wr(phydev, 0); in vsc85xx_sd6g_config_v2()
649 return phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc85xx_sd6g_config_v2()