Lines Matching full:val
27 static int phy_ts_base_write(struct phy_device *phydev, u32 regnum, u16 val) in phy_ts_base_write() argument
33 val); in phy_ts_base_write()
67 u32 val, cnt = 0; in vsc85xx_ts_read_csr() local
92 val = phy_ts_base_read(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL); in vsc85xx_ts_read_csr()
93 } while (!(val & BIU_ADDR_EXE) && cnt++ < BIU_ADDR_CNT_MAX); in vsc85xx_ts_read_csr()
95 val = phy_ts_base_read(phydev, MSCC_PHY_TS_CSR_DATA_MSB); in vsc85xx_ts_read_csr()
96 val <<= 16; in vsc85xx_ts_read_csr()
97 val |= phy_ts_base_read(phydev, MSCC_PHY_TS_CSR_DATA_LSB); in vsc85xx_ts_read_csr()
103 return val; in vsc85xx_ts_read_csr()
107 u16 addr, u32 val) in vsc85xx_ts_write_csr() argument
111 u32 reg, bypass, cnt = 0, lower = val & 0xffff, upper = val >> 16; in vsc85xx_ts_write_csr()
190 u32 val = 0; in vsc85xx_ts_fsb_init() local
193 val = (val << 6) | sig_sel[pos]; in vsc85xx_ts_fsb_init()
196 val); in vsc85xx_ts_fsb_init()
247 u32 val, ingr_latency, egr_latency; in vsc85xx_ts_set_latencies() local
277 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_ts_set_latencies()
279 val |= PHY_PTP_INGR_TSP_CTRL_LOAD_DELAYS; in vsc85xx_ts_set_latencies()
281 val); in vsc85xx_ts_set_latencies()
286 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL); in vsc85xx_ts_set_latencies()
287 val |= PHY_PTP_EGR_TSP_CTRL_LOAD_DELAYS; in vsc85xx_ts_set_latencies()
288 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL, val); in vsc85xx_ts_set_latencies()
346 u32 val; in vsc85xx_ts_eth_cmp1_sig() local
348 val = vsc85xx_ts_read_csr(phydev, EGRESS, MSCC_PHY_ANA_ETH1_NTX_PROT); in vsc85xx_ts_eth_cmp1_sig()
349 val &= ~ANA_ETH1_NTX_PROT_SIG_OFF_MASK; in vsc85xx_ts_eth_cmp1_sig()
350 val |= ANA_ETH1_NTX_PROT_SIG_OFF(0); in vsc85xx_ts_eth_cmp1_sig()
351 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_ETH1_NTX_PROT, val); in vsc85xx_ts_eth_cmp1_sig()
353 val = vsc85xx_ts_read_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_CFG); in vsc85xx_ts_eth_cmp1_sig()
354 val &= ~ANA_FSB_ADDR_FROM_BLOCK_SEL_MASK; in vsc85xx_ts_eth_cmp1_sig()
355 val |= ANA_FSB_ADDR_FROM_ETH1; in vsc85xx_ts_eth_cmp1_sig()
356 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_CFG, val); in vsc85xx_ts_eth_cmp1_sig()
513 u32 val; in vsc85xx_ptp_cmp_init() local
521 val = vsc85xx_ts_read_csr(phydev, blk, in vsc85xx_ptp_cmp_init()
523 val &= ~PTP_FLOW_DOMAIN_RANGE_ENA; in vsc85xx_ptp_cmp_init()
525 MSCC_ANA_PTP_FLOW_DOMAIN_RANGE(i), val); in vsc85xx_ptp_cmp_init()
543 u32 val; in vsc85xx_eth_cmp1_init() local
561 val = vsc85xx_ts_read_csr(phydev, blk, in vsc85xx_eth_cmp1_init()
563 val &= ~ANA_ETH1_FLOW_MATCH_VLAN_TAG_MASK; in vsc85xx_eth_cmp1_init()
564 val |= ANA_ETH1_FLOW_MATCH_VLAN_VERIFY; in vsc85xx_eth_cmp1_init()
566 val); in vsc85xx_eth_cmp1_init()
575 u32 val; in vsc85xx_ip_cmp1_init() local
586 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0)); in vsc85xx_ip_cmp1_init()
587 val &= ~IP1_FLOW_ENA_CHANNEL_MASK_MASK; in vsc85xx_ip_cmp1_init()
588 val |= base ? IP1_FLOW_VALID_CH0 : IP1_FLOW_VALID_CH1; in vsc85xx_ip_cmp1_init()
589 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0), val); in vsc85xx_ip_cmp1_init()
616 u32 val; in vsc85xx_adjfine() local
625 val = PTP_AUTO_ADJ_NS_ROLLOVER(adj); in vsc85xx_adjfine()
626 val |= scaled_ppm > 0 ? PTP_AUTO_ADJ_ADD_1NS : PTP_AUTO_ADJ_SUB_1NS; in vsc85xx_adjfine()
630 /* Update the ppb val in nano seconds to the auto adjust reg. */ in vsc85xx_adjfine()
632 val); in vsc85xx_adjfine()
634 /* The auto adjust update val is set to 0 after write operation. */ in vsc85xx_adjfine()
635 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL); in vsc85xx_adjfine()
636 val |= PTP_LTC_CTRL_AUTO_ADJ_UPDATE; in vsc85xx_adjfine()
637 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in vsc85xx_adjfine()
651 u32 val; in __vsc85xx_gettime() local
653 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL); in __vsc85xx_gettime()
654 val |= PTP_LTC_CTRL_SAVE_ENA; in __vsc85xx_gettime()
655 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in __vsc85xx_gettime()
663 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc85xx_gettime()
666 ts->tv_sec = ((time64_t)val) << 32; in __vsc85xx_gettime()
668 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc85xx_gettime()
670 ts->tv_sec += val; in __vsc85xx_gettime()
702 u32 val; in __vsc85xx_settime() local
711 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL); in __vsc85xx_settime()
712 val |= PTP_LTC_CTRL_LOAD_ENA; in __vsc85xx_settime()
713 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in __vsc85xx_settime()
721 val &= ~PTP_LTC_CTRL_LOAD_ENA; in __vsc85xx_settime()
722 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in __vsc85xx_settime()
749 u32 val; in vsc85xx_adjtime() local
770 val = PTP_LTC_OFFSET_VAL(abs(delta)) | PTP_LTC_OFFSET_ADJ; in vsc85xx_adjtime()
772 val |= PTP_LTC_OFFSET_ADD; in vsc85xx_adjtime()
773 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_OFFSET, val); in vsc85xx_adjtime()
783 u32 val; in vsc85xx_eth1_next_comp() local
785 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT); in vsc85xx_eth1_next_comp()
786 val &= ~ANA_ETH1_NTX_PROT_COMPARATOR_MASK; in vsc85xx_eth1_next_comp()
787 val |= next_comp; in vsc85xx_eth1_next_comp()
788 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT, val); in vsc85xx_eth1_next_comp()
790 val = ANA_ETH1_NXT_PROT_ETYPE_MATCH(etype) | in vsc85xx_eth1_next_comp()
793 MSCC_PHY_ANA_ETH1_NXT_PROT_ETYPE_MATCH, val); in vsc85xx_eth1_next_comp()
810 u32 val; in vsc85xx_ts_ptp_action_flow() local
813 val = PTP_FLOW_PTP_0_FIELD_PTP_FRAME | PTP_FLOW_PTP_0_FIELD_RSVRD_CHECK; in vsc85xx_ts_ptp_action_flow()
815 MSCC_ANA_PTP_FLOW_PTP_0_FIELD(flow), val); in vsc85xx_ts_ptp_action_flow()
817 val = PTP_FLOW_PTP_ACTION_CORR_OFFSET(8) | in vsc85xx_ts_ptp_action_flow()
822 val |= PTP_FLOW_PTP_ACTION_SAVE_LOCAL_TIME; in vsc85xx_ts_ptp_action_flow()
824 val |= PTP_FLOW_PTP_ACTION_MOD_FRAME_STATUS_UPDATE | in vsc85xx_ts_ptp_action_flow()
827 val); in vsc85xx_ts_ptp_action_flow()
831 val = PTP_FLOW_PTP_ACTION2_REWRITE_OFFSET(34) | in vsc85xx_ts_ptp_action_flow()
835 val = PTP_FLOW_PTP_ACTION2_REWRITE_OFFSET(0) | in vsc85xx_ts_ptp_action_flow()
839 val = PTP_FLOW_PTP_ACTION2_REWRITE_OFFSET(16) | in vsc85xx_ts_ptp_action_flow()
842 MSCC_ANA_PTP_FLOW_PTP_ACTION2(flow), val); in vsc85xx_ts_ptp_action_flow()
854 u32 val; in vsc85xx_ptp_conf() local
869 val = vsc85xx_ts_read_csr(phydev, blk, in vsc85xx_ptp_conf()
871 val &= ~PTP_FLOW_ENA; in vsc85xx_ptp_conf()
873 val |= PTP_FLOW_ENA; in vsc85xx_ptp_conf()
875 val); in vsc85xx_ptp_conf()
885 u32 val = ANA_ETH1_FLOW_ADDR_MATCH2_DEST; in vsc85xx_eth1_conf() local
891 val |= ANA_ETH1_FLOW_ADDR_MATCH2_FULL_ADDR | in vsc85xx_eth1_conf()
894 MSCC_ANA_ETH1_FLOW_ADDR_MATCH2(0), val); in vsc85xx_eth1_conf()
899 val |= ANA_ETH1_FLOW_ADDR_MATCH2_ANY_MULTICAST; in vsc85xx_eth1_conf()
901 MSCC_ANA_ETH1_FLOW_ADDR_MATCH2(0), val); in vsc85xx_eth1_conf()
906 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0)); in vsc85xx_eth1_conf()
907 val &= ~ETH1_FLOW_ENA; in vsc85xx_eth1_conf()
909 val |= ETH1_FLOW_ENA; in vsc85xx_eth1_conf()
910 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0), val); in vsc85xx_eth1_conf()
918 u32 val; in vsc85xx_ip1_conf() local
925 val = ANA_IP1_NXT_PROT_IP_MATCH1_PROT_MASK(0xff) | in vsc85xx_ip1_conf()
929 val); in vsc85xx_ip1_conf()
935 val = vsc85xx_ts_read_csr(phydev, blk, in vsc85xx_ip1_conf()
937 val &= ~(IP1_NXT_PROT_UDP_CHKSUM_OFF_MASK | in vsc85xx_ip1_conf()
939 val |= IP1_NXT_PROT_UDP_CHKSUM_WIDTH(2); in vsc85xx_ip1_conf()
941 val &= ~(IP1_NXT_PROT_UDP_CHKSUM_UPDATE | in vsc85xx_ip1_conf()
946 val |= IP1_NXT_PROT_UDP_CHKSUM_OFF(26) | IP1_NXT_PROT_UDP_CHKSUM_CLEAR; in vsc85xx_ip1_conf()
948 val); in vsc85xx_ip1_conf()
950 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0)); in vsc85xx_ip1_conf()
951 val &= ~(IP1_FLOW_MATCH_ADDR_MASK | IP1_FLOW_ENA); in vsc85xx_ip1_conf()
952 val |= IP1_FLOW_MATCH_DEST_SRC_ADDR; in vsc85xx_ip1_conf()
954 val |= IP1_FLOW_ENA; in vsc85xx_ip1_conf()
955 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0), val); in vsc85xx_ip1_conf()
965 u32 val; in vsc85xx_ts_engine_init() local
969 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_ts_engine_init()
972 val &= ~(PTP_ANALYZER_MODE_EGR_ENA(BIT(eng_id)) | in vsc85xx_ts_engine_init()
975 val); in vsc85xx_ts_engine_init()
1010 val &= ~PTP_ANALYZER_MODE_EGR_ENA(BIT(eng_id)); in vsc85xx_ts_engine_init()
1012 val |= PTP_ANALYZER_MODE_EGR_ENA(BIT(eng_id)); in vsc85xx_ts_engine_init()
1014 val &= ~PTP_ANALYZER_MODE_INGR_ENA(BIT(eng_id)); in vsc85xx_ts_engine_init()
1016 val |= PTP_ANALYZER_MODE_INGR_ENA(BIT(eng_id)); in vsc85xx_ts_engine_init()
1019 val); in vsc85xx_ts_engine_init()
1035 u32 val; in vsc85xx_ts_reset_fifo() local
1037 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_ts_reset_fifo()
1039 val |= PTP_EGR_TS_FIFO_RESET; in vsc85xx_ts_reset_fifo()
1041 val); in vsc85xx_ts_reset_fifo()
1043 val &= ~PTP_EGR_TS_FIFO_RESET; in vsc85xx_ts_reset_fifo()
1045 val); in vsc85xx_ts_reset_fifo()
1056 u32 val; in vsc85xx_hwtstamp() local
1093 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_hwtstamp()
1095 val &= ~PTP_INGR_PREDICTOR_EN; in vsc85xx_hwtstamp()
1097 val); in vsc85xx_hwtstamp()
1098 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_hwtstamp()
1100 val &= ~PTP_EGR_PREDICTOR_EN; in vsc85xx_hwtstamp()
1102 val); in vsc85xx_hwtstamp()
1105 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL); in vsc85xx_hwtstamp()
1106 val &= ~(PTP_IFACE_CTRL_EGR_BYPASS | PTP_IFACE_CTRL_INGR_BYPASS); in vsc85xx_hwtstamp()
1108 val |= PTP_IFACE_CTRL_EGR_BYPASS; in vsc85xx_hwtstamp()
1110 val |= PTP_IFACE_CTRL_INGR_BYPASS; in vsc85xx_hwtstamp()
1111 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val); in vsc85xx_hwtstamp()
1119 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_hwtstamp()
1121 val |= PTP_INGR_PREDICTOR_EN; in vsc85xx_hwtstamp()
1123 val); in vsc85xx_hwtstamp()
1124 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_hwtstamp()
1126 val |= PTP_EGR_PREDICTOR_EN; in vsc85xx_hwtstamp()
1128 val); in vsc85xx_hwtstamp()
1268 u32 val; in __vsc8584_init_ptp() local
1289 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1291 val &= ~PTP_INGR_PREDICTOR_EN; in __vsc8584_init_ptp()
1293 val); in __vsc8584_init_ptp()
1294 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1296 val &= ~PTP_EGR_PREDICTOR_EN; in __vsc8584_init_ptp()
1298 val); in __vsc8584_init_ptp()
1301 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL); in __vsc8584_init_ptp()
1302 val &= ~PTP_LTC_CTRL_CLK_SEL_MASK; in __vsc8584_init_ptp()
1303 val |= PTP_LTC_CTRL_CLK_SEL_INTERNAL_250; in __vsc8584_init_ptp()
1304 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in __vsc8584_init_ptp()
1306 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQUENCE); in __vsc8584_init_ptp()
1307 val &= ~PTP_LTC_SEQUENCE_A_MASK; in __vsc8584_init_ptp()
1308 val |= PTP_LTC_SEQUENCE_A(ltc_seq_a[PHC_CLK_250MHZ]); in __vsc8584_init_ptp()
1309 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQUENCE, val); in __vsc8584_init_ptp()
1311 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQ); in __vsc8584_init_ptp()
1312 val &= ~(PTP_LTC_SEQ_ERR_MASK | PTP_LTC_SEQ_ADD_SUB); in __vsc8584_init_ptp()
1314 val |= PTP_LTC_SEQ_ADD_SUB; in __vsc8584_init_ptp()
1315 val |= PTP_LTC_SEQ_ERR(ltc_seq_e[PHC_CLK_250MHZ]); in __vsc8584_init_ptp()
1316 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQ, val); in __vsc8584_init_ptp()
1332 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1334 val &= ~(PTP_ACCUR_PPS_OUT_BYPASS | PTP_ACCUR_PPS_IN_BYPASS | in __vsc8584_init_ptp()
1337 val |= PTP_ACCUR_PPS_OUT_CALIB_ERR | PTP_ACCUR_PPS_OUT_CALIB_DONE | in __vsc8584_init_ptp()
1343 val); in __vsc8584_init_ptp()
1345 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1347 val |= PTP_ACCUR_CALIB_TRIGG; in __vsc8584_init_ptp()
1349 val); in __vsc8584_init_ptp()
1351 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1353 val &= ~PTP_ACCUR_CALIB_TRIGG; in __vsc8584_init_ptp()
1354 val |= PTP_ACCUR_PPS_OUT_CALIB_ERR | PTP_ACCUR_PPS_OUT_CALIB_DONE | in __vsc8584_init_ptp()
1360 val); in __vsc8584_init_ptp()
1362 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1364 val |= PTP_ACCUR_CALIB_TRIGG; in __vsc8584_init_ptp()
1366 val); in __vsc8584_init_ptp()
1368 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1370 val &= ~PTP_ACCUR_CALIB_TRIGG; in __vsc8584_init_ptp()
1372 val); in __vsc8584_init_ptp()
1375 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1377 val &= ~PTP_TSTAMP_FIFO_SI_EN; in __vsc8584_init_ptp()
1379 val); in __vsc8584_init_ptp()
1381 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1383 val &= ~PTP_INGR_REWRITER_REDUCE_PREAMBLE; in __vsc8584_init_ptp()
1385 val); in __vsc8584_init_ptp()
1386 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1388 val &= ~PTP_EGR_REWRITER_REDUCE_PREAMBLE; in __vsc8584_init_ptp()
1390 val); in __vsc8584_init_ptp()
1393 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1395 val |= PTP_INGR_REWRITER_FLAG_BIT_OFF(7) | PTP_INGR_REWRITER_FLAG_VAL; in __vsc8584_init_ptp()
1397 val); in __vsc8584_init_ptp()
1398 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1400 val |= PTP_EGR_REWRITER_FLAG_BIT_OFF(7); in __vsc8584_init_ptp()
1401 val &= ~PTP_EGR_REWRITER_FLAG_VAL; in __vsc8584_init_ptp()
1403 val); in __vsc8584_init_ptp()
1408 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1410 val |= PHY_PTP_INGR_TSP_CTRL_FRACT_NS; in __vsc8584_init_ptp()
1412 val); in __vsc8584_init_ptp()
1414 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL); in __vsc8584_init_ptp()
1415 val |= PHY_PTP_EGR_TSP_CTRL_FRACT_NS; in __vsc8584_init_ptp()
1416 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL, val); in __vsc8584_init_ptp()
1418 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1420 val |= PTP_SERIAL_TOD_IFACE_LS_AUTO_CLR; in __vsc8584_init_ptp()
1422 val); in __vsc8584_init_ptp()
1427 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1429 val &= ~(PTP_EGR_TS_FIFO_SIG_BYTES_MASK | PTP_EGR_TS_FIFO_THRESH_MASK); in __vsc8584_init_ptp()
1431 val |= PTP_EGR_TS_FIFO_SIG_BYTES(16) | PTP_EGR_TS_FIFO_THRESH(7); in __vsc8584_init_ptp()
1433 val); in __vsc8584_init_ptp()
1437 val = PTP_IFACE_CTRL_CLK_ENA; in __vsc8584_init_ptp()
1439 val |= PTP_IFACE_CTRL_GMII_PROT; in __vsc8584_init_ptp()
1440 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val); in __vsc8584_init_ptp()
1444 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_VERSION_CODE); in __vsc8584_init_ptp()
1446 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL); in __vsc8584_init_ptp()
1447 val |= PTP_IFACE_CTRL_EGR_BYPASS; in __vsc8584_init_ptp()
1448 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val); in __vsc8584_init_ptp()
1453 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1456 val &= ~(PTP_ANALYZER_MODE_EGR_ENA_MASK | in __vsc8584_init_ptp()
1463 val |= PTP_ANA_SPLIT_ENCAP_FLOW | PTP_ANA_INGR_ENCAP_FLOW_MODE(0x7) | in __vsc8584_init_ptp()
1466 val); in __vsc8584_init_ptp()