Lines Matching full:phydev
113 static int vsc85xx_phy_read_page(struct phy_device *phydev) in vsc85xx_phy_read_page() argument
115 return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS); in vsc85xx_phy_read_page()
118 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page) in vsc85xx_phy_write_page() argument
120 return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page); in vsc85xx_phy_write_page()
123 static int vsc85xx_get_sset_count(struct phy_device *phydev) in vsc85xx_get_sset_count() argument
125 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_sset_count()
133 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data) in vsc85xx_get_strings() argument
135 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_strings()
145 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i) in vsc85xx_get_stat() argument
147 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_stat()
150 val = phy_read_paged(phydev, priv->hw_stats[i].page, in vsc85xx_get_stat()
161 static void vsc85xx_get_stats(struct phy_device *phydev, in vsc85xx_get_stats() argument
164 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_stats()
171 data[i] = vsc85xx_get_stat(phydev, i); in vsc85xx_get_stats()
174 static int vsc85xx_led_cntl_set(struct phy_device *phydev, in vsc85xx_led_cntl_set() argument
181 mutex_lock(&phydev->lock); in vsc85xx_led_cntl_set()
182 reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL); in vsc85xx_led_cntl_set()
185 rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val); in vsc85xx_led_cntl_set()
186 mutex_unlock(&phydev->lock); in vsc85xx_led_cntl_set()
191 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix) in vsc85xx_mdix_get() argument
195 reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL); in vsc85xx_mdix_get()
204 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix) in vsc85xx_mdix_set() argument
209 reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL); in vsc85xx_mdix_set()
219 rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val); in vsc85xx_mdix_set()
230 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED, in vsc85xx_mdix_set()
236 return genphy_restart_aneg(phydev); in vsc85xx_mdix_set()
239 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count) in vsc85xx_downshift_get() argument
243 reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED, in vsc85xx_downshift_get()
257 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count) in vsc85xx_downshift_set() argument
263 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n"); in vsc85xx_downshift_set()
270 return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED, in vsc85xx_downshift_set()
275 static int vsc85xx_wol_set(struct phy_device *phydev, in vsc85xx_wol_set() argument
278 const u8 *mac_addr = phydev->attached_dev->dev_addr; in vsc85xx_wol_set()
285 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2); in vsc85xx_wol_set()
287 return phy_restore_page(phydev, rc, rc); in vsc85xx_wol_set()
294 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]); in vsc85xx_wol_set()
295 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]); in vsc85xx_wol_set()
296 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]); in vsc85xx_wol_set()
298 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0); in vsc85xx_wol_set()
299 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0); in vsc85xx_wol_set()
300 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0); in vsc85xx_wol_set()
307 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]); in vsc85xx_wol_set()
308 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]); in vsc85xx_wol_set()
309 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]); in vsc85xx_wol_set()
311 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0); in vsc85xx_wol_set()
312 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0); in vsc85xx_wol_set()
313 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0); in vsc85xx_wol_set()
316 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); in vsc85xx_wol_set()
321 __phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val); in vsc85xx_wol_set()
323 rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); in vsc85xx_wol_set()
329 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); in vsc85xx_wol_set()
331 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); in vsc85xx_wol_set()
336 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); in vsc85xx_wol_set()
338 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); in vsc85xx_wol_set()
343 reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_wol_set()
348 static void vsc85xx_wol_get(struct phy_device *phydev, in vsc85xx_wol_get() argument
357 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2); in vsc85xx_wol_get()
361 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); in vsc85xx_wol_get()
365 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD); in vsc85xx_wol_get()
366 pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD); in vsc85xx_wol_get()
367 pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD); in vsc85xx_wol_get()
376 phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); in vsc85xx_wol_get()
380 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) in vsc85xx_edge_rate_magic_get() argument
384 struct device *dev = &phydev->mdio.dev; in vsc85xx_edge_rate_magic_get()
406 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, in vsc85xx_dt_led_mode_get() argument
410 struct vsc8531_private *priv = phydev->priv; in vsc85xx_dt_led_mode_get()
411 struct device *dev = &phydev->mdio.dev; in vsc85xx_dt_led_mode_get()
422 phydev_err(phydev, "DT %s invalid\n", led); in vsc85xx_dt_led_mode_get()
430 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) in vsc85xx_edge_rate_magic_get() argument
435 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, in vsc85xx_dt_led_mode_get() argument
443 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev, in vsc85xx_dt_led_modes_get() argument
446 struct vsc8531_private *priv = phydev->priv; in vsc85xx_dt_led_modes_get()
455 ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop, in vsc85xx_dt_led_modes_get()
465 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate) in vsc85xx_edge_rate_cntl_set() argument
469 mutex_lock(&phydev->lock); in vsc85xx_edge_rate_cntl_set()
470 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, in vsc85xx_edge_rate_cntl_set()
473 mutex_unlock(&phydev->lock); in vsc85xx_edge_rate_cntl_set()
478 static int vsc85xx_mac_if_set(struct phy_device *phydev, in vsc85xx_mac_if_set() argument
484 mutex_lock(&phydev->lock); in vsc85xx_mac_if_set()
485 reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); in vsc85xx_mac_if_set()
505 rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val); in vsc85xx_mac_if_set()
509 rc = genphy_soft_reset(phydev); in vsc85xx_mac_if_set()
512 mutex_unlock(&phydev->lock); in vsc85xx_mac_if_set()
524 static int vsc85xx_update_rgmii_cntl(struct phy_device *phydev, u32 rgmii_cntl, in vsc85xx_update_rgmii_cntl() argument
531 struct device *dev = &phydev->mdio.dev; in vsc85xx_update_rgmii_cntl()
547 if (phy_interface_is_rgmii(phydev)) in vsc85xx_update_rgmii_cntl()
550 rx_delay = phy_get_internal_delay(phydev, dev, vsc85xx_internal_delay, in vsc85xx_update_rgmii_cntl()
553 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || in vsc85xx_update_rgmii_cntl()
554 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in vsc85xx_update_rgmii_cntl()
560 tx_delay = phy_get_internal_delay(phydev, dev, vsc85xx_internal_delay, in vsc85xx_update_rgmii_cntl()
563 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || in vsc85xx_update_rgmii_cntl()
564 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in vsc85xx_update_rgmii_cntl()
574 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, in vsc85xx_update_rgmii_cntl()
580 static int vsc85xx_default_config(struct phy_device *phydev) in vsc85xx_default_config() argument
582 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in vsc85xx_default_config()
584 return vsc85xx_update_rgmii_cntl(phydev, VSC8502_RGMII_CNTL, in vsc85xx_default_config()
589 static int vsc85xx_get_tunable(struct phy_device *phydev, in vsc85xx_get_tunable() argument
594 return vsc85xx_downshift_get(phydev, (u8 *)data); in vsc85xx_get_tunable()
600 static int vsc85xx_set_tunable(struct phy_device *phydev, in vsc85xx_set_tunable() argument
606 return vsc85xx_downshift_set(phydev, *(u8 *)data); in vsc85xx_set_tunable()
613 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val) in vsc85xx_tr_write() argument
615 __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16); in vsc85xx_tr_write()
616 __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); in vsc85xx_tr_write()
617 __phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); in vsc85xx_tr_write()
620 static int vsc8531_pre_init_seq_set(struct phy_device *phydev) in vsc8531_pre_init_seq_set() argument
632 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_STANDARD, in vsc8531_pre_init_seq_set()
637 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, in vsc8531_pre_init_seq_set()
641 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, in vsc8531_pre_init_seq_set()
645 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, in vsc8531_pre_init_seq_set()
650 mutex_lock(&phydev->lock); in vsc8531_pre_init_seq_set()
651 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR); in vsc8531_pre_init_seq_set()
656 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val); in vsc8531_pre_init_seq_set()
659 oldpage = phy_restore_page(phydev, oldpage, oldpage); in vsc8531_pre_init_seq_set()
660 mutex_unlock(&phydev->lock); in vsc8531_pre_init_seq_set()
665 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev) in vsc85xx_eee_init_seq_set() argument
690 mutex_lock(&phydev->lock); in vsc85xx_eee_init_seq_set()
691 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR); in vsc85xx_eee_init_seq_set()
696 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val); in vsc85xx_eee_init_seq_set()
699 oldpage = phy_restore_page(phydev, oldpage, oldpage); in vsc85xx_eee_init_seq_set()
700 mutex_unlock(&phydev->lock); in vsc85xx_eee_init_seq_set()
705 /* phydev->bus->mdio_lock should be locked when using this function */
706 int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val) in phy_base_write() argument
708 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) { in phy_base_write()
709 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n"); in phy_base_write()
713 return __phy_package_write(phydev, VSC88XX_BASE_ADDR, regnum, val); in phy_base_write()
716 /* phydev->bus->mdio_lock should be locked when using this function */
717 int phy_base_read(struct phy_device *phydev, u32 regnum) in phy_base_read() argument
719 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) { in phy_base_read()
720 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n"); in phy_base_read()
724 return __phy_package_read(phydev, VSC88XX_BASE_ADDR, regnum); in phy_base_read()
727 u32 vsc85xx_csr_read(struct phy_device *phydev, in vsc85xx_csr_read() argument
733 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL); in vsc85xx_csr_read()
743 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, in vsc85xx_csr_read()
753 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, in vsc85xx_csr_read()
762 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); in vsc85xx_csr_read()
770 val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17); in vsc85xx_csr_read()
773 val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18); in vsc85xx_csr_read()
775 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc85xx_csr_read()
781 int vsc85xx_csr_write(struct phy_device *phydev, in vsc85xx_csr_write() argument
786 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL); in vsc85xx_csr_write()
796 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, in vsc85xx_csr_write()
800 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val); in vsc85xx_csr_write()
803 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16)); in vsc85xx_csr_write()
812 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, in vsc85xx_csr_write()
821 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); in vsc85xx_csr_write()
828 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc85xx_csr_write()
835 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val) in vsc8584_csr_write() argument
837 phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16); in vsc8584_csr_write()
838 phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); in vsc8584_csr_write()
839 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); in vsc8584_csr_write()
843 int vsc8584_cmd(struct phy_device *phydev, u16 val) in vsc8584_cmd() argument
848 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_cmd()
851 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val); in vsc8584_cmd()
855 reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD); in vsc8584_cmd()
860 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_cmd()
872 static int vsc8584_micro_deassert_reset(struct phy_device *phydev, in vsc8584_micro_deassert_reset() argument
877 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_micro_deassert_reset()
889 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM); in vsc8584_micro_deassert_reset()
895 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
897 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
899 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_micro_deassert_reset()
905 static int vsc8584_micro_assert_reset(struct phy_device *phydev) in vsc8584_micro_assert_reset() argument
910 ret = vsc8584_cmd(phydev, PROC_CMD_NOP); in vsc8584_micro_assert_reset()
914 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_micro_assert_reset()
917 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8584_micro_assert_reset()
919 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); in vsc8584_micro_assert_reset()
921 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b); in vsc8584_micro_assert_reset()
922 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b); in vsc8584_micro_assert_reset()
924 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8584_micro_assert_reset()
926 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); in vsc8584_micro_assert_reset()
928 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP); in vsc8584_micro_assert_reset()
930 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
932 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
934 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF | in vsc8584_micro_assert_reset()
938 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8584_micro_assert_reset()
940 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); in vsc8584_micro_assert_reset()
942 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_micro_assert_reset()
948 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size, in vsc8584_get_fw_crc() argument
953 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); in vsc8584_get_fw_crc()
955 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start); in vsc8584_get_fw_crc()
956 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size); in vsc8584_get_fw_crc()
959 ret = vsc8584_cmd(phydev, PROC_CMD_CRC16); in vsc8584_get_fw_crc()
963 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); in vsc8584_get_fw_crc()
965 *crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2); in vsc8584_get_fw_crc()
968 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_get_fw_crc()
974 static int vsc8584_patch_fw(struct phy_device *phydev, in vsc8584_patch_fw() argument
979 ret = vsc8584_micro_assert_reset(phydev); in vsc8584_patch_fw()
981 dev_err(&phydev->mdio.dev, in vsc8584_patch_fw()
986 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_patch_fw()
992 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM | in vsc8584_patch_fw()
995 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN | in vsc8584_patch_fw()
997 phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000); in vsc8584_patch_fw()
1000 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | in vsc8584_patch_fw()
1004 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM); in vsc8584_patch_fw()
1006 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_patch_fw()
1012 static bool vsc8574_is_serdes_init(struct phy_device *phydev) in vsc8574_is_serdes_init() argument
1017 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8574_is_serdes_init()
1020 reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1)); in vsc8574_is_serdes_init()
1026 reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1)); in vsc8574_is_serdes_init()
1032 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8574_is_serdes_init()
1038 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
1047 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_is_serdes_init()
1053 static int vsc8574_config_pre_init(struct phy_device *phydev) in vsc8574_config_pre_init() argument
1119 struct device *dev = &phydev->mdio.dev; in vsc8574_config_pre_init()
1126 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_config_pre_init()
1129 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8574_config_pre_init()
1131 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8574_config_pre_init()
1133 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc8574_config_pre_init()
1140 phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040); in vsc8574_config_pre_init()
1142 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8574_config_pre_init()
1144 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320); in vsc8574_config_pre_init()
1145 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00); in vsc8574_config_pre_init()
1146 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca); in vsc8574_config_pre_init()
1147 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20); in vsc8574_config_pre_init()
1149 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8574_config_pre_init()
1151 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8574_config_pre_init()
1153 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8574_config_pre_init()
1156 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); in vsc8574_config_pre_init()
1158 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); in vsc8574_config_pre_init()
1160 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); in vsc8574_config_pre_init()
1162 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8574_config_pre_init()
1165 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); in vsc8574_config_pre_init()
1167 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8574_config_pre_init()
1169 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8574_config_pre_init()
1171 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8574_config_pre_init()
1173 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_config_pre_init()
1176 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8574_config_pre_init()
1178 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8574_config_pre_init()
1188 ret = vsc8584_get_fw_crc(phydev, in vsc8574_config_pre_init()
1195 serdes_init = vsc8574_is_serdes_init(phydev); in vsc8574_config_pre_init()
1198 ret = vsc8584_micro_assert_reset(phydev); in vsc8574_config_pre_init()
1211 if (vsc8584_patch_fw(phydev, fw)) in vsc8574_config_pre_init()
1217 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
1220 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7); in vsc8574_config_pre_init()
1221 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012); in vsc8574_config_pre_init()
1222 phy_base_write(phydev, MSCC_INT_MEM_CNTL, in vsc8574_config_pre_init()
1225 vsc8584_micro_deassert_reset(phydev, false); in vsc8574_config_pre_init()
1230 ret = vsc8584_get_fw_crc(phydev, in vsc8574_config_pre_init()
1241 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
1244 ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT | in vsc8574_config_pre_init()
1248 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_config_pre_init()
1256 static void vsc8584_pll5g_cfg2_wr(struct phy_device *phydev, in vsc8584_pll5g_cfg2_wr() argument
1261 rd_dat = vsc85xx_csr_read(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2); in vsc8584_pll5g_cfg2_wr()
1264 vsc85xx_csr_write(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2, rd_dat); in vsc8584_pll5g_cfg2_wr()
1268 static int vsc8584_mcb_rd_trig(struct phy_device *phydev, in vsc8584_mcb_rd_trig() argument
1274 vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr, in vsc8584_mcb_rd_trig()
1280 phydev, MACRO_CTRL, mcb_reg_addr); in vsc8584_mcb_rd_trig()
1284 static int vsc8584_mcb_wr_trig(struct phy_device *phydev, in vsc8584_mcb_wr_trig() argument
1291 vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr, in vsc8584_mcb_wr_trig()
1297 phydev, MACRO_CTRL, mcb_reg_addr); in vsc8584_mcb_wr_trig()
1301 static int vsc8584_pll5g_reset(struct phy_device *phydev) in vsc8584_pll5g_reset() argument
1306 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1312 vsc8584_pll5g_cfg2_wr(phydev, dis_fsm); in vsc8584_pll5g_reset()
1315 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1323 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1329 vsc8584_pll5g_cfg2_wr(phydev, dis_fsm); in vsc8584_pll5g_reset()
1332 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1342 static int vsc8584_config_pre_init(struct phy_device *phydev) in vsc8584_config_pre_init() argument
1374 struct device *dev = &phydev->mdio.dev; in vsc8584_config_pre_init()
1379 ret = vsc8584_pll5g_reset(phydev); in vsc8584_config_pre_init()
1385 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_config_pre_init()
1388 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8584_config_pre_init()
1390 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8584_config_pre_init()
1392 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc8584_config_pre_init()
1394 reg = phy_base_read(phydev, MSCC_PHY_BYPASS_CONTROL); in vsc8584_config_pre_init()
1396 phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg); in vsc8584_config_pre_init()
1403 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3); in vsc8584_config_pre_init()
1405 phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000); in vsc8584_config_pre_init()
1407 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8584_config_pre_init()
1409 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20); in vsc8584_config_pre_init()
1411 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8584_config_pre_init()
1413 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8584_config_pre_init()
1415 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8584_config_pre_init()
1417 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4)); in vsc8584_config_pre_init()
1419 reg = phy_base_read(phydev, MSCC_PHY_TR_MSB); in vsc8584_config_pre_init()
1422 phy_base_write(phydev, MSCC_PHY_TR_MSB, reg); in vsc8584_config_pre_init()
1424 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4)); in vsc8584_config_pre_init()
1427 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); in vsc8584_config_pre_init()
1429 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); in vsc8584_config_pre_init()
1431 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); in vsc8584_config_pre_init()
1433 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8584_config_pre_init()
1436 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); in vsc8584_config_pre_init()
1438 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8584_config_pre_init()
1440 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8584_config_pre_init()
1442 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8584_config_pre_init()
1444 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_config_pre_init()
1447 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8584_config_pre_init()
1449 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8584_config_pre_init()
1459 ret = vsc8584_get_fw_crc(phydev, in vsc8584_config_pre_init()
1467 if (vsc8584_patch_fw(phydev, fw)) in vsc8584_config_pre_init()
1472 vsc8584_micro_deassert_reset(phydev, false); in vsc8584_config_pre_init()
1475 ret = vsc8584_get_fw_crc(phydev, in vsc8584_config_pre_init()
1485 ret = vsc8584_micro_assert_reset(phydev); in vsc8584_config_pre_init()
1490 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_GPIO); in vsc8584_config_pre_init()
1492 ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg); in vsc8584_config_pre_init()
1497 ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg); in vsc8584_config_pre_init()
1501 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8584_config_pre_init()
1503 ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); in vsc8584_config_pre_init()
1507 vsc8584_micro_deassert_reset(phydev, true); in vsc8584_config_pre_init()
1510 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_config_pre_init()
1517 static void vsc8584_get_base_addr(struct phy_device *phydev) in vsc8584_get_base_addr() argument
1519 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8584_get_base_addr()
1522 phy_lock_mdio_bus(phydev); in vsc8584_get_base_addr()
1523 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); in vsc8584_get_base_addr()
1525 addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4); in vsc8584_get_base_addr()
1528 val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL); in vsc8584_get_base_addr()
1530 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_get_base_addr()
1531 phy_unlock_mdio_bus(phydev); in vsc8584_get_base_addr()
1537 vsc8531->ts_base_addr = phydev->mdio.addr; in vsc8584_get_base_addr()
1541 vsc8531->base_addr = phydev->mdio.addr + addr; in vsc8584_get_base_addr()
1547 vsc8531->base_addr = phydev->mdio.addr - addr; in vsc8584_get_base_addr()
1557 static void vsc85xx_coma_mode_release(struct phy_device *phydev) in vsc85xx_coma_mode_release() argument
1566 vsc85xx_phy_write_page(phydev, MSCC_PHY_PAGE_EXTENDED_GPIO); in vsc85xx_coma_mode_release()
1567 __phy_modify(phydev, MSCC_PHY_GPIO_CONTROL_2, in vsc85xx_coma_mode_release()
1569 vsc85xx_phy_write_page(phydev, MSCC_PHY_PAGE_STANDARD); in vsc85xx_coma_mode_release()
1572 static int vsc8584_config_host_serdes(struct phy_device *phydev) in vsc8584_config_host_serdes() argument
1574 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8584_config_host_serdes()
1578 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_config_host_serdes()
1583 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); in vsc8584_config_host_serdes()
1585 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) { in vsc8584_config_host_serdes()
1587 } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in vsc8584_config_host_serdes()
1594 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); in vsc8584_config_host_serdes()
1598 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_config_host_serdes()
1605 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) in vsc8584_config_host_serdes()
1610 ret = vsc8584_cmd(phydev, val); in vsc8584_config_host_serdes()
1617 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | in vsc8584_config_host_serdes()
1626 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | in vsc8584_config_host_serdes()
1634 return vsc85xx_sd6g_config_v2(phydev); in vsc8584_config_host_serdes()
1637 static int vsc8574_config_host_serdes(struct phy_device *phydev) in vsc8574_config_host_serdes() argument
1639 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8574_config_host_serdes()
1643 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_host_serdes()
1648 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); in vsc8574_config_host_serdes()
1650 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) { in vsc8574_config_host_serdes()
1652 } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in vsc8574_config_host_serdes()
1654 } else if (phy_interface_is_rgmii(phydev)) { in vsc8574_config_host_serdes()
1661 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); in vsc8574_config_host_serdes()
1665 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_host_serdes()
1670 if (!phy_interface_is_rgmii(phydev)) { in vsc8574_config_host_serdes()
1673 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) in vsc8574_config_host_serdes()
1678 ret = vsc8584_cmd(phydev, val); in vsc8574_config_host_serdes()
1686 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | in vsc8574_config_host_serdes()
1695 return vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | in vsc8574_config_host_serdes()
1702 static int vsc8584_config_init(struct phy_device *phydev) in vsc8584_config_init() argument
1704 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8584_config_init()
1708 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in vsc8584_config_init()
1710 phy_lock_mdio_bus(phydev); in vsc8584_config_init()
1725 if (phy_package_init_once(phydev)) { in vsc8584_config_init()
1730 WARN_ON(phydev->drv->phy_id_mask & 0xf); in vsc8584_config_init()
1732 switch (phydev->phy_id & phydev->drv->phy_id_mask) { in vsc8584_config_init()
1737 ret = vsc8574_config_pre_init(phydev); in vsc8584_config_init()
1740 ret = vsc8574_config_host_serdes(phydev); in vsc8584_config_init()
1748 ret = vsc8584_config_pre_init(phydev); in vsc8584_config_init()
1751 ret = vsc8584_config_host_serdes(phydev); in vsc8584_config_init()
1754 vsc85xx_coma_mode_release(phydev); in vsc8584_config_init()
1765 phy_unlock_mdio_bus(phydev); in vsc8584_config_init()
1767 ret = vsc8584_macsec_init(phydev); in vsc8584_config_init()
1771 ret = vsc8584_ptp_init(phydev); in vsc8584_config_init()
1775 val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); in vsc8584_config_init()
1779 ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val); in vsc8584_config_init()
1783 ret = vsc85xx_update_rgmii_cntl(phydev, VSC8572_RGMII_CNTL, in vsc8584_config_init()
1789 ret = genphy_soft_reset(phydev); in vsc8584_config_init()
1794 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); in vsc8584_config_init()
1802 phy_unlock_mdio_bus(phydev); in vsc8584_config_init()
1806 static irqreturn_t vsc8584_handle_interrupt(struct phy_device *phydev) in vsc8584_handle_interrupt() argument
1811 irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc8584_handle_interrupt()
1818 ret = vsc8584_handle_ts_interrupt(phydev); in vsc8584_handle_interrupt()
1823 vsc8584_handle_macsec_interrupt(phydev); in vsc8584_handle_interrupt()
1826 phy_trigger_machine(phydev); in vsc8584_handle_interrupt()
1831 static int vsc85xx_config_init(struct phy_device *phydev) in vsc85xx_config_init() argument
1834 struct vsc8531_private *vsc8531 = phydev->priv; in vsc85xx_config_init()
1836 rc = vsc85xx_default_config(phydev); in vsc85xx_config_init()
1840 rc = vsc85xx_mac_if_set(phydev, phydev->interface); in vsc85xx_config_init()
1844 rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic); in vsc85xx_config_init()
1848 phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask; in vsc85xx_config_init()
1851 rc = vsc8531_pre_init_seq_set(phydev); in vsc85xx_config_init()
1856 rc = vsc85xx_eee_init_seq_set(phydev); in vsc85xx_config_init()
1861 rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); in vsc85xx_config_init()
1869 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb, in __phy_write_mcb_s6g() argument
1876 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, reg, in __phy_write_mcb_s6g()
1884 val = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, reg); in __phy_write_mcb_s6g()
1898 int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) in phy_update_mcb_s6g() argument
1900 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ); in phy_update_mcb_s6g()
1904 int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) in phy_commit_mcb_s6g() argument
1906 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE); in phy_commit_mcb_s6g()
1909 static int vsc8514_config_host_serdes(struct phy_device *phydev) in vsc8514_config_host_serdes() argument
1914 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8514_config_host_serdes()
1919 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); in vsc8514_config_host_serdes()
1922 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); in vsc8514_config_host_serdes()
1926 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8514_config_host_serdes()
1931 ret = vsc8584_cmd(phydev, PROC_CMD_NOP); in vsc8514_config_host_serdes()
1935 ret = vsc8584_cmd(phydev, in vsc8514_config_host_serdes()
1940 dev_err(&phydev->mdio.dev, "%s: QSGMII error: %d\n", in vsc8514_config_host_serdes()
1952 vsc8584_micro_assert_reset(phydev); in vsc8514_config_host_serdes()
1953 val = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8514_config_host_serdes()
1956 ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, val); in vsc8514_config_host_serdes()
1958 vsc8584_micro_deassert_reset(phydev, false); in vsc8514_config_host_serdes()
1960 return vsc85xx_sd6g_config_v2(phydev); in vsc8514_config_host_serdes()
1963 static int vsc8514_config_pre_init(struct phy_device *phydev) in vsc8514_config_pre_init() argument
1991 struct device *dev = &phydev->mdio.dev; in vsc8514_config_pre_init()
1996 ret = vsc8584_pll5g_reset(phydev); in vsc8514_config_pre_init()
2002 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8514_config_pre_init()
2005 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8514_config_pre_init()
2007 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8514_config_pre_init()
2009 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8514_config_pre_init()
2011 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8514_config_pre_init()
2013 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8514_config_pre_init()
2015 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8514_config_pre_init()
2018 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); in vsc8514_config_pre_init()
2020 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8514_config_pre_init()
2022 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8514_config_pre_init()
2024 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8514_config_pre_init()
2026 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8514_config_pre_init()
2028 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8514_config_pre_init()
2030 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8514_config_pre_init()
2038 vsc8584_micro_deassert_reset(phydev, false); in vsc8514_config_pre_init()
2040 vsc8584_micro_assert_reset(phydev); in vsc8514_config_pre_init()
2041 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8514_config_pre_init()
2045 ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg); in vsc8514_config_pre_init()
2050 ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg); in vsc8514_config_pre_init()
2053 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8514_config_pre_init()
2055 ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); in vsc8514_config_pre_init()
2062 vsc8584_micro_deassert_reset(phydev, false); in vsc8514_config_pre_init()
2066 vsc8584_micro_deassert_reset(phydev, false); in vsc8514_config_pre_init()
2070 static int vsc8514_config_init(struct phy_device *phydev) in vsc8514_config_init() argument
2072 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8514_config_init()
2075 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in vsc8514_config_init()
2077 phy_lock_mdio_bus(phydev); in vsc8514_config_init()
2090 if (phy_package_init_once(phydev)) { in vsc8514_config_init()
2091 ret = vsc8514_config_pre_init(phydev); in vsc8514_config_init()
2094 ret = vsc8514_config_host_serdes(phydev); in vsc8514_config_init()
2097 vsc85xx_coma_mode_release(phydev); in vsc8514_config_init()
2100 phy_unlock_mdio_bus(phydev); in vsc8514_config_init()
2102 ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK, in vsc8514_config_init()
2108 ret = genphy_soft_reset(phydev); in vsc8514_config_init()
2114 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); in vsc8514_config_init()
2122 phy_unlock_mdio_bus(phydev); in vsc8514_config_init()
2126 static int vsc85xx_ack_interrupt(struct phy_device *phydev) in vsc85xx_ack_interrupt() argument
2130 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in vsc85xx_ack_interrupt()
2131 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_ack_interrupt()
2136 static int vsc85xx_config_intr(struct phy_device *phydev) in vsc85xx_config_intr() argument
2140 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in vsc85xx_config_intr()
2141 rc = vsc85xx_ack_interrupt(phydev); in vsc85xx_config_intr()
2145 vsc8584_config_macsec_intr(phydev); in vsc85xx_config_intr()
2146 vsc8584_config_ts_intr(phydev); in vsc85xx_config_intr()
2148 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, in vsc85xx_config_intr()
2151 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc85xx_config_intr()
2154 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_config_intr()
2158 rc = vsc85xx_ack_interrupt(phydev); in vsc85xx_config_intr()
2164 static irqreturn_t vsc85xx_handle_interrupt(struct phy_device *phydev) in vsc85xx_handle_interrupt() argument
2168 irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_handle_interrupt()
2170 phy_error(phydev); in vsc85xx_handle_interrupt()
2177 phy_trigger_machine(phydev); in vsc85xx_handle_interrupt()
2182 static int vsc85xx_config_aneg(struct phy_device *phydev) in vsc85xx_config_aneg() argument
2186 rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl); in vsc85xx_config_aneg()
2190 return genphy_config_aneg(phydev); in vsc85xx_config_aneg()
2193 static int vsc85xx_read_status(struct phy_device *phydev) in vsc85xx_read_status() argument
2197 rc = vsc85xx_mdix_get(phydev, &phydev->mdix); in vsc85xx_read_status()
2201 return genphy_read_status(phydev); in vsc85xx_read_status()
2204 static int vsc8514_probe(struct phy_device *phydev) in vsc8514_probe() argument
2211 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc8514_probe()
2215 phydev->priv = vsc8531; in vsc8514_probe()
2217 vsc8584_get_base_addr(phydev); in vsc8514_probe()
2218 devm_phy_package_join(&phydev->mdio.dev, phydev, in vsc8514_probe()
2225 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc8514_probe()
2230 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc8514_probe()
2233 static int vsc8574_probe(struct phy_device *phydev) in vsc8574_probe() argument
2240 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc8574_probe()
2244 phydev->priv = vsc8531; in vsc8574_probe()
2246 vsc8584_get_base_addr(phydev); in vsc8574_probe()
2247 devm_phy_package_join(&phydev->mdio.dev, phydev, in vsc8574_probe()
2254 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc8574_probe()
2259 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc8574_probe()
2262 static int vsc8584_probe(struct phy_device *phydev) in vsc8584_probe() argument
2270 if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) { in vsc8584_probe()
2271 dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n"); in vsc8584_probe()
2275 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc8584_probe()
2279 phydev->priv = vsc8531; in vsc8584_probe()
2281 vsc8584_get_base_addr(phydev); in vsc8584_probe()
2282 devm_phy_package_join(&phydev->mdio.dev, phydev, vsc8531->base_addr, in vsc8584_probe()
2289 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc8584_probe()
2294 if (phy_package_probe_once(phydev)) { in vsc8584_probe()
2295 ret = vsc8584_ptp_probe_once(phydev); in vsc8584_probe()
2300 ret = vsc8584_ptp_probe(phydev); in vsc8584_probe()
2304 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc8584_probe()
2307 static int vsc85xx_probe(struct phy_device *phydev) in vsc85xx_probe() argument
2314 rate_magic = vsc85xx_edge_rate_magic_get(phydev); in vsc85xx_probe()
2318 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc85xx_probe()
2322 phydev->priv = vsc8531; in vsc85xx_probe()
2329 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc85xx_probe()
2334 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc85xx_probe()