Lines Matching full:phydev
280 static int cal_cycle(struct phy_device *phydev, int devad, in cal_cycle() argument
286 phy_modify_mmd(phydev, devad, regnum, in cal_cycle()
288 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, in cal_cycle()
291 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, in cal_cycle()
297 phydev_err(phydev, "Calibration cycle timeout\n"); in cal_cycle()
301 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, in cal_cycle()
303 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP); in cal_cycle()
307 phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); in cal_cycle()
312 static int rext_fill_result(struct phy_device *phydev, u16 *buf) in rext_fill_result() argument
314 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, in rext_fill_result()
316 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, in rext_fill_result()
322 static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) in rext_cal_efuse() argument
328 rext_fill_result(phydev, rext_cal_val); in rext_cal_efuse()
333 static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) in tx_offset_fill_result() argument
335 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, in tx_offset_fill_result()
337 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, in tx_offset_fill_result()
339 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, in tx_offset_fill_result()
341 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, in tx_offset_fill_result()
347 static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) in tx_offset_cal_efuse() argument
356 tx_offset_fill_result(phydev, tx_offset_cal_val); in tx_offset_cal_efuse()
361 static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) in tx_amp_fill_result() argument
374 switch (phydev->drv->phy_id) { in tx_amp_fill_result()
395 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, in tx_amp_fill_result()
399 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, in tx_amp_fill_result()
403 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, in tx_amp_fill_result()
407 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, in tx_amp_fill_result()
412 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, in tx_amp_fill_result()
416 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, in tx_amp_fill_result()
420 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, in tx_amp_fill_result()
424 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, in tx_amp_fill_result()
429 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, in tx_amp_fill_result()
433 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, in tx_amp_fill_result()
437 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, in tx_amp_fill_result()
441 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, in tx_amp_fill_result()
446 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, in tx_amp_fill_result()
450 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, in tx_amp_fill_result()
454 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, in tx_amp_fill_result()
458 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, in tx_amp_fill_result()
466 static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) in tx_amp_cal_efuse() argument
474 tx_amp_fill_result(phydev, tx_amp_cal_val); in tx_amp_cal_efuse()
479 static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, in tx_r50_fill_result() argument
485 if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) in tx_r50_fill_result()
507 phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); in tx_r50_fill_result()
512 static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, in tx_r50_cal_efuse() argument
533 tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); in tx_r50_cal_efuse()
538 static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) in tx_vcm_cal_sw() argument
544 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, in tx_vcm_cal_sw()
546 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, in tx_vcm_cal_sw()
548 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, in tx_vcm_cal_sw()
553 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
556 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
559 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
564 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
567 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
570 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
575 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
578 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
581 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
586 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
589 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
592 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
604 phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); in tx_vcm_cal_sw()
607 ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, in tx_vcm_cal_sw()
626 lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
636 upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
657 cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, in tx_vcm_cal_sw()
664 phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); in tx_vcm_cal_sw()
668 cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, in tx_vcm_cal_sw()
675 phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", in tx_vcm_cal_sw()
680 phydev_warn(phydev, in tx_vcm_cal_sw()
688 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, in tx_vcm_cal_sw()
690 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, in tx_vcm_cal_sw()
692 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, in tx_vcm_cal_sw()
694 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, in tx_vcm_cal_sw()
701 static void mt798x_phy_common_finetune(struct phy_device *phydev) in mt798x_phy_common_finetune() argument
703 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); in mt798x_phy_common_finetune()
705 __phy_write(phydev, 0x11, 0xc71); in mt798x_phy_common_finetune()
706 __phy_write(phydev, 0x12, 0xc); in mt798x_phy_common_finetune()
707 __phy_write(phydev, 0x10, 0x8fae); in mt798x_phy_common_finetune()
710 __phy_write(phydev, 0x11, 0x2f00); in mt798x_phy_common_finetune()
711 __phy_write(phydev, 0x12, 0xe); in mt798x_phy_common_finetune()
712 __phy_write(phydev, 0x10, 0x8fb0); in mt798x_phy_common_finetune()
715 __phy_write(phydev, 0x11, 0x55a0); in mt798x_phy_common_finetune()
716 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_common_finetune()
717 __phy_write(phydev, 0x10, 0x83aa); in mt798x_phy_common_finetune()
720 __phy_write(phydev, 0x11, 0x240); in mt798x_phy_common_finetune()
721 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_common_finetune()
722 __phy_write(phydev, 0x10, 0x9680); in mt798x_phy_common_finetune()
725 __phy_write(phydev, 0x11, 0x0); in mt798x_phy_common_finetune()
726 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_common_finetune()
727 __phy_write(phydev, 0x10, 0x9686); in mt798x_phy_common_finetune()
735 __phy_write(phydev, 0x11, 0xbaef); in mt798x_phy_common_finetune()
736 __phy_write(phydev, 0x12, 0x2e); in mt798x_phy_common_finetune()
737 __phy_write(phydev, 0x10, 0x968c); in mt798x_phy_common_finetune()
738 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); in mt798x_phy_common_finetune()
741 static void mt7981_phy_finetune(struct phy_device *phydev) in mt7981_phy_finetune() argument
756 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); in mt7981_phy_finetune()
759 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); in mt7981_phy_finetune()
761 __phy_write(phydev, 0x11, 0x600); in mt7981_phy_finetune()
762 __phy_write(phydev, 0x12, 0x0); in mt7981_phy_finetune()
763 __phy_write(phydev, 0x10, 0x8fc0); in mt7981_phy_finetune()
766 __phy_write(phydev, 0x11, 0x4c2a); in mt7981_phy_finetune()
767 __phy_write(phydev, 0x12, 0x3e); in mt7981_phy_finetune()
768 __phy_write(phydev, 0x10, 0x8fa4); in mt7981_phy_finetune()
773 __phy_write(phydev, 0x11, 0xd10a); in mt7981_phy_finetune()
774 __phy_write(phydev, 0x12, 0x34); in mt7981_phy_finetune()
775 __phy_write(phydev, 0x10, 0x8f82); in mt7981_phy_finetune()
778 __phy_write(phydev, 0x11, 0x5555); in mt7981_phy_finetune()
779 __phy_write(phydev, 0x12, 0x55); in mt7981_phy_finetune()
780 __phy_write(phydev, 0x10, 0x8ec0); in mt7981_phy_finetune()
781 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); in mt7981_phy_finetune()
784 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, in mt7981_phy_finetune()
790 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); in mt7981_phy_finetune()
793 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); in mt7981_phy_finetune()
794 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); in mt7981_phy_finetune()
795 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); in mt7981_phy_finetune()
796 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); in mt7981_phy_finetune()
797 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); in mt7981_phy_finetune()
798 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); in mt7981_phy_finetune()
799 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); in mt7981_phy_finetune()
800 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); in mt7981_phy_finetune()
801 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); in mt7981_phy_finetune()
802 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); in mt7981_phy_finetune()
805 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, in mt7981_phy_finetune()
807 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, in mt7981_phy_finetune()
811 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); in mt7981_phy_finetune()
812 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); in mt7981_phy_finetune()
814 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); in mt7981_phy_finetune()
817 static void mt7988_phy_finetune(struct phy_device *phydev) in mt7988_phy_finetune() argument
826 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); in mt7988_phy_finetune()
829 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); in mt7988_phy_finetune()
831 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); in mt7988_phy_finetune()
833 __phy_write(phydev, 0x11, 0x500); in mt7988_phy_finetune()
834 __phy_write(phydev, 0x12, 0x0); in mt7988_phy_finetune()
835 __phy_write(phydev, 0x10, 0x8fc0); in mt7988_phy_finetune()
842 __phy_write(phydev, 0x11, 0xb90a); in mt7988_phy_finetune()
843 __phy_write(phydev, 0x12, 0x6f); in mt7988_phy_finetune()
844 __phy_write(phydev, 0x10, 0x8f82); in mt7988_phy_finetune()
847 __phy_write(phydev, 0x11, 0xfbba); in mt7988_phy_finetune()
848 __phy_write(phydev, 0x12, 0xc3); in mt7988_phy_finetune()
849 __phy_write(phydev, 0x10, 0x87f8); in mt7988_phy_finetune()
851 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); in mt7988_phy_finetune()
854 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, in mt7988_phy_finetune()
860 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff); in mt7988_phy_finetune()
863 static void mt798x_phy_eee(struct phy_device *phydev) in mt798x_phy_eee() argument
865 phy_modify_mmd(phydev, MDIO_MMD_VEND1, in mt798x_phy_eee()
872 phy_modify_mmd(phydev, MDIO_MMD_VEND1, in mt798x_phy_eee()
878 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in mt798x_phy_eee()
882 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in mt798x_phy_eee()
885 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in mt798x_phy_eee()
888 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, in mt798x_phy_eee()
894 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, in mt798x_phy_eee()
898 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, in mt798x_phy_eee()
903 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, in mt798x_phy_eee()
910 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, in mt798x_phy_eee()
914 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, in mt798x_phy_eee()
919 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, in mt798x_phy_eee()
925 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); in mt798x_phy_eee()
927 __phy_write(phydev, 0x11, 0xb); in mt798x_phy_eee()
928 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_eee()
929 __phy_write(phydev, 0x10, 0x9690); in mt798x_phy_eee()
932 __phy_write(phydev, 0x11, 0x114f); in mt798x_phy_eee()
933 __phy_write(phydev, 0x12, 0x2); in mt798x_phy_eee()
934 __phy_write(phydev, 0x10, 0x969a); in mt798x_phy_eee()
937 __phy_write(phydev, 0x11, 0x3028); in mt798x_phy_eee()
938 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_eee()
939 __phy_write(phydev, 0x10, 0x969e); in mt798x_phy_eee()
942 __phy_write(phydev, 0x11, 0x5010); in mt798x_phy_eee()
943 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_eee()
944 __phy_write(phydev, 0x10, 0x96a0); in mt798x_phy_eee()
947 __phy_write(phydev, 0x11, 0x24a); in mt798x_phy_eee()
948 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_eee()
949 __phy_write(phydev, 0x10, 0x96a8); in mt798x_phy_eee()
952 __phy_write(phydev, 0x11, 0x3210); in mt798x_phy_eee()
953 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_eee()
954 __phy_write(phydev, 0x10, 0x96b8); in mt798x_phy_eee()
957 __phy_write(phydev, 0x11, 0x1463); in mt798x_phy_eee()
958 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_eee()
959 __phy_write(phydev, 0x10, 0x96ca); in mt798x_phy_eee()
962 __phy_write(phydev, 0x11, 0x36); in mt798x_phy_eee()
963 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_eee()
964 __phy_write(phydev, 0x10, 0x8f80); in mt798x_phy_eee()
965 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); in mt798x_phy_eee()
967 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); in mt798x_phy_eee()
968 __phy_modify(phydev, MTK_PHY_LPI_REG_14, in mt798x_phy_eee()
972 __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, in mt798x_phy_eee()
974 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); in mt798x_phy_eee()
976 phy_modify_mmd(phydev, MDIO_MMD_VEND1, in mt798x_phy_eee()
983 static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, in cal_sw() argument
993 ret = tx_vcm_cal_sw(phydev, pair_n); in cal_sw()
1004 static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, in cal_efuse() argument
1014 ret = rext_cal_efuse(phydev, buf); in cal_efuse()
1017 ret = tx_offset_cal_efuse(phydev, buf); in cal_efuse()
1020 ret = tx_amp_cal_efuse(phydev, buf); in cal_efuse()
1023 ret = tx_r50_cal_efuse(phydev, buf, pair_n); in cal_efuse()
1035 static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, in start_cal() argument
1043 ret = cal_efuse(phydev, cal_item, start_pair, in start_cal()
1047 ret = cal_sw(phydev, cal_item, start_pair, end_pair); in start_cal()
1054 phydev_err(phydev, "cal %d failed\n", cal_item); in start_cal()
1061 static int mt798x_phy_calibration(struct phy_device *phydev) in mt798x_phy_calibration() argument
1068 cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); in mt798x_phy_calibration()
1081 phydev_err(phydev, "invalid efuse data\n"); in mt798x_phy_calibration()
1086 ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); in mt798x_phy_calibration()
1089 ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); in mt798x_phy_calibration()
1092 ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); in mt798x_phy_calibration()
1095 ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); in mt798x_phy_calibration()
1098 ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); in mt798x_phy_calibration()
1107 static int mt798x_phy_config_init(struct phy_device *phydev) in mt798x_phy_config_init() argument
1109 switch (phydev->drv->phy_id) { in mt798x_phy_config_init()
1111 mt7981_phy_finetune(phydev); in mt798x_phy_config_init()
1114 mt7988_phy_finetune(phydev); in mt798x_phy_config_init()
1118 mt798x_phy_common_finetune(phydev); in mt798x_phy_config_init()
1119 mt798x_phy_eee(phydev); in mt798x_phy_config_init()
1121 return mt798x_phy_calibration(phydev); in mt798x_phy_config_init()
1124 static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index, in mt798x_phy_led_blink_set() argument
1135 err = mtk_phy_hw_led_blink_set(phydev, index, blinking); in mt798x_phy_led_blink_set()
1139 return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK, in mt798x_phy_led_blink_set()
1143 static int mt798x_phy_led_brightness_set(struct phy_device *phydev, in mt798x_phy_led_brightness_set() argument
1148 err = mtk_phy_hw_led_blink_set(phydev, index, false); in mt798x_phy_led_brightness_set()
1152 return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK, in mt798x_phy_led_brightness_set()
1166 static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, in mt798x_phy_led_hw_is_supported() argument
1169 return mtk_phy_led_hw_is_supported(phydev, index, rules, in mt798x_phy_led_hw_is_supported()
1173 static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index, in mt798x_phy_led_hw_control_get() argument
1176 return mtk_phy_led_hw_ctrl_get(phydev, index, rules, in mt798x_phy_led_hw_control_get()
1182 static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index, in mt798x_phy_led_hw_control_set() argument
1185 return mtk_phy_led_hw_ctrl_set(phydev, index, rules, in mt798x_phy_led_hw_control_set()
1191 static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num) in mt7988_phy_led_get_polarity() argument
1193 struct mtk_socphy_shared *priv = phydev->shared->priv; in mt7988_phy_led_get_polarity()
1201 if (polarities & BIT(phydev->mdio.addr)) in mt7988_phy_led_get_polarity()
1207 static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev) in mt7988_phy_fix_leds_polarities() argument
1214 phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? in mt7988_phy_fix_leds_polarities()
1217 mt7988_phy_led_get_polarity(phydev, index) ? in mt7988_phy_fix_leds_polarities()
1221 pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); in mt7988_phy_fix_leds_polarities()
1223 dev_err(&phydev->mdio.bus->dev, in mt7988_phy_fix_leds_polarities()
1229 static int mt7988_phy_probe_shared(struct phy_device *phydev) in mt7988_phy_probe_shared() argument
1231 struct device_node *np = dev_of_node(&phydev->mdio.bus->dev); in mt7988_phy_probe_shared()
1232 struct mtk_socphy_shared *shared = phydev->shared->priv; in mt7988_phy_probe_shared()
1263 static int mt7988_phy_probe(struct phy_device *phydev) in mt7988_phy_probe() argument
1269 if (phydev->mdio.addr > 3) in mt7988_phy_probe()
1272 err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, in mt7988_phy_probe()
1277 if (phy_package_probe_once(phydev)) { in mt7988_phy_probe()
1278 err = mt7988_phy_probe_shared(phydev); in mt7988_phy_probe()
1283 shared = phydev->shared->priv; in mt7988_phy_probe()
1284 priv = &shared->priv[phydev->mdio.addr]; in mt7988_phy_probe()
1286 phydev->priv = priv; in mt7988_phy_probe()
1288 mtk_phy_leds_state_init(phydev); in mt7988_phy_probe()
1290 err = mt7988_phy_fix_leds_polarities(phydev); in mt7988_phy_probe()
1298 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, in mt7988_phy_probe()
1301 return mt798x_phy_calibration(phydev); in mt7988_phy_probe()
1304 static int mt7981_phy_probe(struct phy_device *phydev) in mt7981_phy_probe() argument
1308 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv), in mt7981_phy_probe()
1313 phydev->priv = priv; in mt7981_phy_probe()
1315 mtk_phy_leds_state_init(phydev); in mt7981_phy_probe()
1317 return mt798x_phy_calibration(phydev); in mt7981_phy_probe()