Lines Matching +full:0 +full:x3210
13 #define MTK_GPHY_ID_MT7981 0x03a29461
14 #define MTK_GPHY_ID_MT7988 0x03a29481
16 #define MTK_EXT_PAGE_ACCESS 0x1f
17 #define MTK_PHY_PAGE_STANDARD 0x0000
18 #define MTK_PHY_PAGE_EXTENDED_3 0x0003
20 #define MTK_PHY_LPI_REG_14 0x14
21 #define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0)
23 #define MTK_PHY_LPI_REG_1c 0x1c
26 #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
27 #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
30 #define TXRESERVE_MIN 0
33 #define MTK_PHY_ANARG_RG 0x10
37 #define MTK_PHY_TXVLD_DA_RG 0x12
39 #define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0)
41 #define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16
43 #define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0)
45 #define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17
47 #define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0)
49 #define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18
51 #define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0)
53 #define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19
55 #define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0)
57 #define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20
59 #define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0)
61 #define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21
63 #define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0)
65 #define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22
67 #define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0)
69 #define MTK_PHY_RXADC_CTRL_RG7 0xc6
72 #define MTK_PHY_RXADC_CTRL_RG9 0xc8
76 #define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0)
78 #define MTK_PHY_LDO_OUTPUT_V 0xd7
80 #define MTK_PHY_RG_ANA_CAL_RG0 0xdb
83 #define MTK_PHY_RG_ZCALEN_A BIT(0)
85 #define MTK_PHY_RG_ANA_CAL_RG1 0xdc
89 #define MTK_PHY_RG_TXVOS_CALEN BIT(0)
91 #define MTK_PHY_RG_ANA_CAL_RG5 0xe0
94 #define MTK_PHY_RG_TX_FILTER 0xfe
96 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120
98 #define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0)
100 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122
101 #define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0)
103 #define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144
106 #define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172
108 #define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0)
110 #define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173
112 #define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0)
114 #define MTK_PHY_RG_AD_CAL_COMP 0x17a
117 #define MTK_PHY_RG_AD_CAL_CLK 0x17b
118 #define MTK_PHY_DA_CAL_CLK BIT(0)
120 #define MTK_PHY_RG_AD_CALIN 0x17c
121 #define MTK_PHY_DA_CALIN_FLAG BIT(0)
123 #define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d
124 #define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0)
126 #define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e
127 #define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0)
129 #define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f
130 #define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0)
132 #define MTK_PHY_RG_DASN_DAC_IN0_D 0x180
133 #define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0)
135 #define MTK_PHY_RG_DASN_DAC_IN1_A 0x181
136 #define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0)
138 #define MTK_PHY_RG_DASN_DAC_IN1_B 0x182
139 #define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0)
141 #define MTK_PHY_RG_DASN_DAC_IN1_C 0x183
142 #define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0)
144 #define MTK_PHY_RG_DASN_DAC_IN1_D 0x184
145 #define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0)
147 #define MTK_PHY_RG_DEV1E_REG19b 0x19b
150 #define MTK_PHY_RG_LP_IIR2_K1_L 0x22a
151 #define MTK_PHY_RG_LP_IIR2_K1_U 0x22b
152 #define MTK_PHY_RG_LP_IIR2_K2_L 0x22c
153 #define MTK_PHY_RG_LP_IIR2_K2_U 0x22d
154 #define MTK_PHY_RG_LP_IIR2_K3_L 0x22e
155 #define MTK_PHY_RG_LP_IIR2_K3_U 0x22f
156 #define MTK_PHY_RG_LP_IIR2_K4_L 0x230
157 #define MTK_PHY_RG_LP_IIR2_K4_U 0x231
158 #define MTK_PHY_RG_LP_IIR2_K5_L 0x232
159 #define MTK_PHY_RG_LP_IIR2_K5_U 0x233
161 #define MTK_PHY_RG_DEV1E_REG234 0x234
162 #define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0)
166 #define MTK_PHY_RG_LPF_CNT_VAL 0x235
168 #define MTK_PHY_RG_DEV1E_REG238 0x238
169 #define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0)
172 #define MTK_PHY_RG_DEV1E_REG239 0x239
173 #define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0)
176 #define MTK_PHY_RG_DEV1E_REG27C 0x27c
178 #define MTK_PHY_RG_DEV1E_REG27D 0x27d
179 #define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0)
181 #define MTK_PHY_RG_DEV1E_REG2C7 0x2c7
182 #define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0)
185 #define MTK_PHY_RG_DEV1E_REG2D1 0x2d1
186 #define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0)
191 #define MTK_PHY_RG_DEV1E_REG323 0x323
192 #define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0)
195 #define MTK_PHY_RG_DEV1E_REG324 0x324
196 #define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0)
199 #define MTK_PHY_RG_DEV1E_REG326 0x326
200 #define MTK_PHY_LPI_MODE_SD_ON BIT(0)
206 #define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502
207 #define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503
209 #define MTK_PHY_DA_TX_R50_PAIR_A 0x53d
210 #define MTK_PHY_DA_TX_R50_PAIR_B 0x53e
211 #define MTK_PHY_DA_TX_R50_PAIR_C 0x53f
212 #define MTK_PHY_DA_TX_R50_PAIR_D 0x540
217 #define MTK_PHY_RG_BG_RASEL 0x115
218 #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)
221 #define RG_GPIO_MISC_TPBANK0 0x6f0
225 #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0))
226 #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0))
227 #define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0))
228 #define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0))
229 #define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0))
231 #define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0))
232 #define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0))
233 #define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0))
234 #define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0))
235 #define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0))
237 #define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0))
238 #define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0))
240 #define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0))
241 #define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0))
304 if (ret < 0) in cal_cycle()
307 phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); in cal_cycle()
315 MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); in rext_fill_result()
319 return 0; in rext_fill_result()
326 rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); in rext_cal_efuse()
330 return 0; in rext_cal_efuse()
336 MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); in tx_offset_fill_result()
344 return 0; in tx_offset_fill_result()
351 tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); in tx_offset_cal_efuse()
358 return 0; in tx_offset_cal_efuse()
388 for (i = 0; i < 12; i++) { in tx_amp_fill_result()
391 bias[i] = 0; in tx_amp_fill_result()
398 buf[0] + bias[0])); in tx_amp_fill_result()
402 buf[0] + bias[1])); in tx_amp_fill_result()
406 buf[0] + bias[2])); in tx_amp_fill_result()
410 buf[0] + bias[3])); in tx_amp_fill_result()
463 return 0; in tx_amp_fill_result()
470 tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); in tx_amp_cal_efuse()
471 tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); in tx_amp_cal_efuse()
472 tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); in tx_amp_cal_efuse()
473 tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); in tx_amp_cal_efuse()
476 return 0; in tx_amp_cal_efuse()
482 int bias = 0; in tx_r50_fill_result()
488 val = clamp_val(bias + tx_r50_cal_val, 0, 63); in tx_r50_fill_result()
509 return 0; in tx_r50_fill_result()
535 return 0; in tx_r50_cal_efuse()
617 } else if (ret == 0) { in tx_vcm_cal_sw()
646 if (ret < 0) in tx_vcm_cal_sw()
655 ret = 0; in tx_vcm_cal_sw()
664 phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); in tx_vcm_cal_sw()
667 ret = 0; in tx_vcm_cal_sw()
675 phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", in tx_vcm_cal_sw()
677 } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && in tx_vcm_cal_sw()
678 lower_ret == 0) { in tx_vcm_cal_sw()
679 ret = 0; in tx_vcm_cal_sw()
681 "TX-VCM SW cal result at high margin 0x%x\n", in tx_vcm_cal_sw()
705 __phy_write(phydev, 0x11, 0xc71); in mt798x_phy_common_finetune()
706 __phy_write(phydev, 0x12, 0xc); in mt798x_phy_common_finetune()
707 __phy_write(phydev, 0x10, 0x8fae); in mt798x_phy_common_finetune()
710 __phy_write(phydev, 0x11, 0x2f00); in mt798x_phy_common_finetune()
711 __phy_write(phydev, 0x12, 0xe); in mt798x_phy_common_finetune()
712 __phy_write(phydev, 0x10, 0x8fb0); in mt798x_phy_common_finetune()
715 __phy_write(phydev, 0x11, 0x55a0); in mt798x_phy_common_finetune()
716 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_common_finetune()
717 __phy_write(phydev, 0x10, 0x83aa); in mt798x_phy_common_finetune()
720 __phy_write(phydev, 0x11, 0x240); in mt798x_phy_common_finetune()
721 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_common_finetune()
722 __phy_write(phydev, 0x10, 0x9680); in mt798x_phy_common_finetune()
724 /* TrFreeze = 0 (mt7988 default) */ in mt798x_phy_common_finetune()
725 __phy_write(phydev, 0x11, 0x0); in mt798x_phy_common_finetune()
726 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_common_finetune()
727 __phy_write(phydev, 0x10, 0x9686); in mt798x_phy_common_finetune()
735 __phy_write(phydev, 0x11, 0xbaef); in mt798x_phy_common_finetune()
736 __phy_write(phydev, 0x12, 0x2e); in mt798x_phy_common_finetune()
737 __phy_write(phydev, 0x10, 0x968c); in mt798x_phy_common_finetune()
738 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); in mt798x_phy_common_finetune()
743 u16 val[8] = { 0x01ce, 0x01c1, in mt7981_phy_finetune()
744 0x020f, 0x0202, in mt7981_phy_finetune()
745 0x03d0, 0x03c0, in mt7981_phy_finetune()
746 0x0013, 0x0005 }; in mt7981_phy_finetune()
753 for (k = 0, i = 1; i < 12; i++) { in mt7981_phy_finetune()
754 if (i % 3 == 0) in mt7981_phy_finetune()
761 __phy_write(phydev, 0x11, 0x600); in mt7981_phy_finetune()
762 __phy_write(phydev, 0x12, 0x0); in mt7981_phy_finetune()
763 __phy_write(phydev, 0x10, 0x8fc0); in mt7981_phy_finetune()
766 __phy_write(phydev, 0x11, 0x4c2a); in mt7981_phy_finetune()
767 __phy_write(phydev, 0x12, 0x3e); in mt7981_phy_finetune()
768 __phy_write(phydev, 0x10, 0x8fa4); in mt7981_phy_finetune()
773 __phy_write(phydev, 0x11, 0xd10a); in mt7981_phy_finetune()
774 __phy_write(phydev, 0x12, 0x34); in mt7981_phy_finetune()
775 __phy_write(phydev, 0x10, 0x8f82); in mt7981_phy_finetune()
778 __phy_write(phydev, 0x11, 0x5555); in mt7981_phy_finetune()
779 __phy_write(phydev, 0x12, 0x55); in mt7981_phy_finetune()
780 __phy_write(phydev, 0x10, 0x8ec0); in mt7981_phy_finetune()
781 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); in mt7981_phy_finetune()
787 BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); in mt7981_phy_finetune()
790 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); in mt7981_phy_finetune()
793 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); in mt7981_phy_finetune()
794 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); in mt7981_phy_finetune()
795 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); in mt7981_phy_finetune()
796 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); in mt7981_phy_finetune()
797 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); in mt7981_phy_finetune()
798 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); in mt7981_phy_finetune()
799 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); in mt7981_phy_finetune()
800 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); in mt7981_phy_finetune()
801 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); in mt7981_phy_finetune()
802 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); in mt7981_phy_finetune()
806 MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); in mt7981_phy_finetune()
808 MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); in mt7981_phy_finetune()
811 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); in mt7981_phy_finetune()
812 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); in mt7981_phy_finetune()
814 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); in mt7981_phy_finetune()
819 u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, in mt7988_phy_finetune()
820 0x020d, 0x0206, 0x0384, 0x03d0, in mt7988_phy_finetune()
821 0x03c6, 0x030a, 0x0011, 0x0005 }; in mt7988_phy_finetune()
825 for (i = 0; i < 12; i++) in mt7988_phy_finetune()
829 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); in mt7988_phy_finetune()
833 __phy_write(phydev, 0x11, 0x500); in mt7988_phy_finetune()
834 __phy_write(phydev, 0x12, 0x0); in mt7988_phy_finetune()
835 __phy_write(phydev, 0x10, 0x8fc0); in mt7988_phy_finetune()
842 __phy_write(phydev, 0x11, 0xb90a); in mt7988_phy_finetune()
843 __phy_write(phydev, 0x12, 0x6f); in mt7988_phy_finetune()
844 __phy_write(phydev, 0x10, 0x8f82); in mt7988_phy_finetune()
847 __phy_write(phydev, 0x11, 0xfbba); in mt7988_phy_finetune()
848 __phy_write(phydev, 0x12, 0xc3); in mt7988_phy_finetune()
849 __phy_write(phydev, 0x10, 0x87f8); in mt7988_phy_finetune()
851 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); in mt7988_phy_finetune()
857 BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa)); in mt7988_phy_finetune()
860 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff); in mt7988_phy_finetune()
869 FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | in mt798x_phy_eee()
870 FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); in mt798x_phy_eee()
876 0xff)); in mt798x_phy_eee()
891 FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); in mt798x_phy_eee()
900 FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | in mt798x_phy_eee()
901 FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); in mt798x_phy_eee()
906 0x33) | in mt798x_phy_eee()
916 FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | in mt798x_phy_eee()
926 /* Regsigdet_sel_1000 = 0 */ in mt798x_phy_eee()
927 __phy_write(phydev, 0x11, 0xb); in mt798x_phy_eee()
928 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_eee()
929 __phy_write(phydev, 0x10, 0x9690); in mt798x_phy_eee()
932 __phy_write(phydev, 0x11, 0x114f); in mt798x_phy_eee()
933 __phy_write(phydev, 0x12, 0x2); in mt798x_phy_eee()
934 __phy_write(phydev, 0x10, 0x969a); in mt798x_phy_eee()
937 __phy_write(phydev, 0x11, 0x3028); in mt798x_phy_eee()
938 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_eee()
939 __phy_write(phydev, 0x10, 0x969e); in mt798x_phy_eee()
942 __phy_write(phydev, 0x11, 0x5010); in mt798x_phy_eee()
943 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_eee()
944 __phy_write(phydev, 0x10, 0x96a0); in mt798x_phy_eee()
947 __phy_write(phydev, 0x11, 0x24a); in mt798x_phy_eee()
948 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_eee()
949 __phy_write(phydev, 0x10, 0x96a8); in mt798x_phy_eee()
952 __phy_write(phydev, 0x11, 0x3210); in mt798x_phy_eee()
953 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_eee()
954 __phy_write(phydev, 0x10, 0x96b8); in mt798x_phy_eee()
956 /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */ in mt798x_phy_eee()
957 __phy_write(phydev, 0x11, 0x1463); in mt798x_phy_eee()
958 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_eee()
959 __phy_write(phydev, 0x10, 0x96ca); in mt798x_phy_eee()
962 __phy_write(phydev, 0x11, 0x36); in mt798x_phy_eee()
963 __phy_write(phydev, 0x12, 0x0); in mt798x_phy_eee()
964 __phy_write(phydev, 0x10, 0x8f80); in mt798x_phy_eee()
965 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); in mt798x_phy_eee()
970 FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); in mt798x_phy_eee()
973 FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); in mt798x_phy_eee()
974 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); in mt798x_phy_eee()
980 0xff)); in mt798x_phy_eee()
1001 return 0; in cal_sw()
1032 return 0; in cal_efuse()
1058 return 0; in start_cal()
1064 int ret = 0; in mt798x_phy_calibration()
1072 return 0; in mt798x_phy_calibration()
1080 if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { in mt798x_phy_calibration()
1132 if (err < 0) in mt798x_phy_led_blink_set()
1196 if (led_num == 0) in mt7988_phy_led_get_polarity()
1213 for (index = 0; index < 2; ++index) in mt7988_phy_fix_leds_polarities()
1218 MTK_PHY_LED_ON_POLARITY : 0); in mt7988_phy_fix_leds_polarities()
1226 return 0; in mt7988_phy_fix_leds_polarities()
1260 return 0; in mt7988_phy_probe_shared()
1272 err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, in mt7988_phy_probe()
1299 MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); in mt7988_phy_probe()