Lines Matching +full:0 +full:x6001
14 #define PHY_ID_88Q2220_REVB0 (MARVELL_PHY_ID_88Q2220 | 0x1)
15 #define PHY_ID_88Q2220_REVB1 (MARVELL_PHY_ID_88Q2220 | 0x2)
16 #define PHY_ID_88Q2220_REVB2 (MARVELL_PHY_ID_88Q2220 | 0x3)
19 #define MDIO_MMD_AN_MV_STAT_ANEG 0x0100
20 #define MDIO_MMD_AN_MV_STAT_LOCAL_RX 0x1000
21 #define MDIO_MMD_AN_MV_STAT_REMOTE_RX 0x2000
22 #define MDIO_MMD_AN_MV_STAT_LOCAL_MASTER 0x4000
23 #define MDIO_MMD_AN_MV_STAT_MS_CONF_FAULT 0x8000
26 #define MDIO_MMD_AN_MV_STAT2_AN_RESOLVED 0x0800
27 #define MDIO_MMD_AN_MV_STAT2_100BT1 0x2000
28 #define MDIO_MMD_AN_MV_STAT2_1000BT1 0x4000
31 #define MDIO_MMD_PCS_MV_INT_EN_LINK_UP 0x0040
32 #define MDIO_MMD_PCS_MV_INT_EN_LINK_DOWN 0x0080
33 #define MDIO_MMD_PCS_MV_INT_EN_100BT1 0x1000
36 #define MDIO_MMD_PCS_MV_GPIO_INT_STAT_LINK_UP 0x0040
37 #define MDIO_MMD_PCS_MV_GPIO_INT_STAT_LINK_DOWN 0x0080
38 #define MDIO_MMD_PCS_MV_GPIO_INT_STAT_100BT1_GEN 0x1000
41 #define MDIO_MMD_PCS_MV_GPIO_INT_CTRL_TRI_DIS 0x0800
44 #define MDIO_MMD_PCS_MV_TEMP_SENSOR1_RAW_INT 0x0001
45 #define MDIO_MMD_PCS_MV_TEMP_SENSOR1_INT 0x0040
46 #define MDIO_MMD_PCS_MV_TEMP_SENSOR1_INT_EN 0x0080
49 #define MDIO_MMD_PCS_MV_TEMP_SENSOR2_DIS_MASK 0xc000
52 #define MDIO_MMD_PCS_MV_TEMP_SENSOR3_INT_THRESH_MASK 0xff00
53 #define MDIO_MMD_PCS_MV_TEMP_SENSOR3_MASK 0x00ff
56 #define MDIO_MMD_PCS_MV_100BT1_STAT1_IDLE_ERROR 0x00ff
57 #define MDIO_MMD_PCS_MV_100BT1_STAT1_JABBER 0x0100
58 #define MDIO_MMD_PCS_MV_100BT1_STAT1_LINK 0x0200
59 #define MDIO_MMD_PCS_MV_100BT1_STAT1_LOCAL_RX 0x1000
60 #define MDIO_MMD_PCS_MV_100BT1_STAT1_REMOTE_RX 0x2000
61 #define MDIO_MMD_PCS_MV_100BT1_STAT1_LOCAL_MASTER 0x4000
64 #define MDIO_MMD_PCS_MV_100BT1_STAT2_JABBER 0x0001
65 #define MDIO_MMD_PCS_MV_100BT1_STAT2_POL 0x0002
66 #define MDIO_MMD_PCS_MV_100BT1_STAT2_LINK 0x0004
67 #define MDIO_MMD_PCS_MV_100BT1_STAT2_ANGE 0x0008
70 #define MDIO_MMD_PCS_MV_100BT1_INT_EN_LINKEVENT 0x0400
73 #define MDIO_MMD_PCS_MV_COPPER_INT_STAT_LINKEVENT 0x0400
78 #define MDIO_MMD_PCS_MV_TDR_RESET_TDR_RST 0x1000
85 #define MDIO_MMD_PCS_MV_TDR_STATUS_MASK 0x0003
86 #define MDIO_MMD_PCS_MV_TDR_STATUS_OFF 0x0001
87 #define MDIO_MMD_PCS_MV_TDR_STATUS_ON 0x0002
88 #define MDIO_MMD_PCS_MV_TDR_STATUS_DIST_MASK 0xff00
89 #define MDIO_MMD_PCS_MV_TDR_STATUS_VCT_STAT_MASK 0x00f0
90 #define MDIO_MMD_PCS_MV_TDR_STATUS_VCT_STAT_SHORT 0x0030
91 #define MDIO_MMD_PCS_MV_TDR_STATUS_VCT_STAT_OPEN 0x00e0
92 #define MDIO_MMD_PCS_MV_TDR_STATUS_VCT_STAT_OK 0x0070
93 #define MDIO_MMD_PCS_MV_TDR_STATUS_VCT_STAT_IN_PROGR 0x0080
94 #define MDIO_MMD_PCS_MV_TDR_STATUS_VCT_STAT_NOISE 0x0050
109 { MDIO_MMD_PCS, 0xffe4, 0x07b5 },
110 { MDIO_MMD_PCS, 0xffe4, 0x06b6 },
114 { MDIO_MMD_PCS, 0xffde, 0x402f },
115 { MDIO_MMD_PCS, 0xfe34, 0x4040 },
116 { MDIO_MMD_PCS, 0xfe2a, 0x3c1d },
117 { MDIO_MMD_PCS, 0xfe34, 0x0040 },
118 { MDIO_MMD_AN, 0x8032, 0x0064 },
119 { MDIO_MMD_AN, 0x8031, 0x0a01 },
120 { MDIO_MMD_AN, 0x8031, 0x0c01 },
121 { MDIO_MMD_PCS, 0xffdb, 0x0010 },
125 { MDIO_MMD_PCS, 0x8033, 0x6801 },
126 { MDIO_MMD_AN, MDIO_AN_T1_CTRL, 0x0 },
129 { MDIO_MMD_PCS, 0xfe1b, 0x48 },
130 { MDIO_MMD_PCS, 0xffe4, 0x6b6 },
131 { MDIO_MMD_PMAPMD, MDIO_CTRL1, 0x0 },
132 { MDIO_MMD_PCS, MDIO_CTRL1, 0x0 },
136 { MDIO_MMD_PCS, 0xfe79, 0x0 },
137 { MDIO_MMD_PCS, 0xfe07, 0x125a },
138 { MDIO_MMD_PCS, 0xfe09, 0x1288 },
139 { MDIO_MMD_PCS, 0xfe08, 0x2588 },
140 { MDIO_MMD_PCS, 0xfe11, 0x1105 },
141 { MDIO_MMD_PCS, 0xfe72, 0x042c },
142 { MDIO_MMD_PCS, 0xfbba, 0xcb2 },
143 { MDIO_MMD_PCS, 0xfbbb, 0xc4a },
144 { MDIO_MMD_AN, 0x8032, 0x2020 },
145 { MDIO_MMD_AN, 0x8031, 0xa28 },
146 { MDIO_MMD_AN, 0x8031, 0xc28 },
147 { MDIO_MMD_PCS, 0xffdb, 0xfc10 },
148 { MDIO_MMD_PCS, 0xfe1b, 0x58 },
149 { MDIO_MMD_PCS, 0xfe79, 0x4 },
150 { MDIO_MMD_PCS, 0xfe5f, 0xe8 },
151 { MDIO_MMD_PCS, 0xfe05, 0x755c },
155 { MDIO_MMD_PCS, 0xffe4, 0x0007 },
156 { MDIO_MMD_AN, MDIO_AN_T1_CTRL, 0x0 },
157 { MDIO_MMD_PCS, 0xffe3, 0x7000 },
158 { MDIO_MMD_PMAPMD, MDIO_CTRL1, 0x0840 },
162 { MDIO_MMD_PCS, 0xffe4, 0x0007 },
163 { MDIO_MMD_AN, MDIO_AN_T1_CTRL, 0x0 },
164 { MDIO_MMD_PMAPMD, MDIO_CTRL1, 0x0840 },
168 { MDIO_MMD_PCS, 0xfe07, 0x125a },
169 { MDIO_MMD_PCS, 0xfe09, 0x1288 },
170 { MDIO_MMD_PCS, 0xfe08, 0x2588 },
171 { MDIO_MMD_PCS, 0xfe72, 0x042c },
172 { MDIO_MMD_PCS, 0xffe4, 0x0071 },
173 { MDIO_MMD_PCS, 0xffe4, 0x0001 },
174 { MDIO_MMD_PCS, 0xfe1b, 0x0048 },
175 { MDIO_MMD_PMAPMD, 0x0000, 0x0000 },
176 { MDIO_MMD_PCS, 0x0000, 0x0000 },
177 { MDIO_MMD_PCS, 0xffdb, 0xfc10 },
178 { MDIO_MMD_PCS, 0xfe1b, 0x58 },
179 { MDIO_MMD_PCS, 0xfcad, 0x030c },
180 { MDIO_MMD_PCS, 0x8032, 0x6001 },
181 { MDIO_MMD_PCS, 0xfdff, 0x05a5 },
182 { MDIO_MMD_PCS, 0xfdec, 0xdbaf },
183 { MDIO_MMD_PCS, 0xfcab, 0x1054 },
184 { MDIO_MMD_PCS, 0xfcac, 0x1483 },
185 { MDIO_MMD_PCS, 0x8033, 0xc801 },
186 { MDIO_MMD_AN, 0x8032, 0x2020 },
187 { MDIO_MMD_AN, 0x8031, 0xa28 },
188 { MDIO_MMD_AN, 0x8031, 0xc28 },
189 { MDIO_MMD_PCS, 0xfbba, 0x0cb2 },
190 { MDIO_MMD_PCS, 0xfbbb, 0x0c4a },
191 { MDIO_MMD_PCS, 0xfe5f, 0xe8 },
192 { MDIO_MMD_PCS, 0xfe05, 0x755c },
193 { MDIO_MMD_PCS, 0xfa20, 0x002a },
194 { MDIO_MMD_PCS, 0xfe11, 0x1105 },
205 if (ret < 0) in mv88q2xxx_write_mmd_vals()
209 return 0; in mv88q2xxx_write_mmd_vals()
219 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe1b, 0x48); in mv88q2xxx_soft_reset()
220 if (ret < 0) in mv88q2xxx_soft_reset()
226 if (ret < 0) in mv88q2xxx_soft_reset()
233 if (ret < 0) in mv88q2xxx_soft_reset()
236 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xffe4, 0xc); in mv88q2xxx_soft_reset()
237 if (ret < 0) in mv88q2xxx_soft_reset()
242 return phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe1b, 0x58); in mv88q2xxx_soft_reset()
244 return 0; in mv88q2xxx_soft_reset()
258 if (ret < 0) { in mv88q2xxx_read_link_gbit()
271 if (ret < 0) in mv88q2xxx_read_link_gbit()
280 if (ret < 0) in mv88q2xxx_read_link_gbit()
289 return 0; in mv88q2xxx_read_link_gbit()
306 if (ret < 0) in mv88q2xxx_read_link_100m()
312 return 0; in mv88q2xxx_read_link_100m()
316 if (ret < 0) in mv88q2xxx_read_link_100m()
323 if (ret < 0) in mv88q2xxx_read_link_100m()
335 return 0; in mv88q2xxx_read_link_100m()
351 return 0; in mv88q2xxx_read_link()
360 if (ret < 0) in mv88q2xxx_read_master_slave_state()
368 return 0; in mv88q2xxx_read_master_slave_state()
377 if (ret < 0) in mv88q2xxx_read_aneg_speed()
381 return 0; in mv88q2xxx_read_aneg_speed()
388 return 0; in mv88q2xxx_read_aneg_speed()
400 if (ret < 0) in mv88q2xxx_read_status()
404 if (ret < 0) in mv88q2xxx_read_status()
408 if (ret < 0) in mv88q2xxx_read_status()
412 if (ret < 0) in mv88q2xxx_read_status()
416 if (ret < 0) in mv88q2xxx_read_status()
421 return 0; in mv88q2xxx_read_status()
425 if (ret < 0) in mv88q2xxx_read_status()
447 return 0; in mv88q2xxx_get_features()
477 return 0; in mv88q2xxx_config_init()
490 if (ret < 0) in mv88q2xxx_get_sqi()
499 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, 0xfc5d, 0xff, 0xac); in mv88q2xxx_get_sqi()
500 if (ret < 0) in mv88q2xxx_get_sqi()
503 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, 0xfc88); in mv88q2xxx_get_sqi()
504 if (ret < 0) in mv88q2xxx_get_sqi()
508 return ret & 0x0f; in mv88q2xxx_get_sqi()
529 if (ret < 0) in mv88q2xxx_config_intr()
538 MDIO_MMD_PCS_MV_INT_EN, 0); in mv88q2xxx_config_intr()
539 if (ret < 0) in mv88q2xxx_config_intr()
543 MDIO_MMD_PCS_MV_100BT1_INT_EN, 0); in mv88q2xxx_config_intr()
561 if (irq < 0) { in mv88q2xxx_handle_interrupt()
571 if (irq < 0) { in mv88q2xxx_handle_interrupt()
639 return 0; in mv88q2xxx_hwmon_is_visible()
654 if (ret < 0) in mv88q2xxx_hwmon_read()
659 return 0; in mv88q2xxx_hwmon_read()
663 if (ret < 0) in mv88q2xxx_hwmon_read()
669 return 0; in mv88q2xxx_hwmon_read()
673 if (ret < 0) in mv88q2xxx_hwmon_read()
677 return 0; in mv88q2xxx_hwmon_read()
739 return 0; in mv88q2xxx_hwmon_probe()
762 if (ret < 0) in mv88q2110_config_init()
769 if (ret < 0) in mv88q2110_config_init()
781 if (ret < 0) in mv88q222x_revb0_config_init()
788 if (ret < 0) in mv88q222x_revb0_config_init()
805 if (ret < 0) in mv88q222x_revb1_revb2_config_init()
812 if (ret < 0) in mv88q222x_revb1_revb2_config_init()
827 MDIO_MMD_PCS_MV_TEMP_SENSOR2_DIS_MASK, 0); in mv88q222x_config_init()
828 if (ret < 0) in mv88q222x_config_init()
843 MDIO_MMD_PCS_MV_TDR_OFF_CUTOFF, 0x0058); in mv88q222x_cable_test_start()
844 if (ret < 0) in mv88q222x_cable_test_start()
848 MDIO_MMD_PCS_MV_TDR_OFF_LONG_CABLE, 0x00eb); in mv88q222x_cable_test_start()
849 if (ret < 0) in mv88q222x_cable_test_start()
853 MDIO_MMD_PCS_MV_TDR_OFF_SHORT_CABLE, 0x010e); in mv88q222x_cable_test_start()
854 if (ret < 0) in mv88q222x_cable_test_start()
858 0x0d90); in mv88q222x_cable_test_start()
859 if (ret < 0) in mv88q222x_cable_test_start()
864 if (ret < 0) in mv88q222x_cable_test_start()
870 return 0; in mv88q222x_cable_test_start()
880 if (status < 0) in mv88q222x_cable_test_get_status()
884 MDIO_MMD_PCS_MV_TDR_RESET_TDR_RST | 0xd90); in mv88q222x_cable_test_get_status()
885 if (ret < 0) in mv88q222x_cable_test_get_status()
918 return 0; in mv88q222x_cable_test_get_status()