36 #define MII_LXT970_IER_IEN	0x0002
49 #define MII_LXT971_IER_IEN	0x00f2
52 #define MII_LXT971_ISR_MASK	0x00f0
68 	if (err < 0)  in lxt970_ack_interrupt()
73 	if (err < 0)  in lxt970_ack_interrupt()
76 	return 0;  in lxt970_ack_interrupt()
90 		err = phy_write(phydev, MII_LXT970_IER, 0);  in lxt970_config_intr()
108 	if (irq_status < 0) {  in lxt970_handle_interrupt()
114 	if (irq_status < 0) {  in lxt970_handle_interrupt()
129 	return phy_write(phydev, MII_LXT970_CONFIG, 0);  in lxt970_config_init()
137 	if (err < 0)  in lxt971_ack_interrupt()
140 	return 0;  in lxt971_ack_interrupt()
154 		err = phy_write(phydev, MII_LXT971_IER, 0);  in lxt971_config_intr()
169 	if (irq_status < 0) {  in lxt971_handle_interrupt()
196 	if (status < 0)  in lxt973a2_update_link()
200 	if (control < 0)  in lxt973a2_update_link()
206 	} while (status >= 0 && retry-- && status == control);  in lxt973a2_update_link()
208 	if (status < 0)  in lxt973a2_update_link()
211 	if ((status & BMSR_LSTATUS) == 0)  in lxt973a2_update_link()
212 		phydev->link = 0;  in lxt973a2_update_link()
216 	return 0;  in lxt973a2_update_link()
235 		if (adv < 0)  in lxt973a2_read_status()
241 			if (lpa < 0)  in lxt973a2_read_status()
255 		phydev->pause = phydev->asym_pause = 0;  in lxt973a2_read_status()
270 		if (err < 0)  in lxt973a2_read_status()
273 		phydev->pause = phydev->asym_pause = 0;  in lxt973a2_read_status()
277 	return 0;  in lxt973a2_read_status()
299 	return 0;  in lxt973_probe()
305 	return phydev->priv ? 0 : genphy_config_aneg(phydev);  in lxt973_config_aneg()
310 	.phy_id		= 0x78100000,
312 	.phy_id_mask	= 0xfffffff0,
318 	.phy_id		= 0x001378e0,
320 	.phy_id_mask	= 0xfffffff0,
327 	.phy_id		= 0x00137a10,
329 	.phy_id_mask	= 0xffffffff,
331 	.flags		= 0,
338 	.phy_id		= 0x00137a10,
340 	.phy_id_mask	= 0xfffffff0,
342 	.flags		= 0,
352 	{ 0x78100000, 0xfffffff0 },
353 	{ 0x001378e0, 0xfffffff0 },
354 	{ 0x00137a10, 0xfffffff0 },