Lines Matching +full:0 +full:xfffffff0
11 #define TI_DP83848C_PHY_ID 0x20005ca0
12 #define TI_DP83620_PHY_ID 0x20005ce0
13 #define NS_DP83848C_PHY_ID 0x20005c90
14 #define TLK10X_PHY_ID 0x2000a210
17 #define DP83848_MICR 0x11 /* MII Interrupt Control Register */
18 #define DP83848_MISR 0x12 /* MII Interrupt Status Register */
21 #define DP83848_MICR_INT_OE BIT(0) /* Interrupt Output Enable */
25 #define DP83848_MISR_RHF_INT_EN BIT(0) /* Receive Error Counter */
58 return err < 0 ? err : 0; in dp83848_ack_interrupt()
66 if (control < 0) in dp83848_config_intr()
78 if (ret < 0) in dp83848_config_intr()
99 if (irq_status < 0) { in dp83848_handle_interrupt()
123 return 0; in dp83848_config_init()
127 { TI_DP83848C_PHY_ID, 0xfffffff0 },
128 { NS_DP83848C_PHY_ID, 0xfffffff0 },
129 { TI_DP83620_PHY_ID, 0xfffffff0 },
130 { TLK10X_PHY_ID, 0xfffffff0 },
138 .phy_id_mask = 0xfffffff0, \