17 #define DP83822_PHY_ID	        0x2000a240
18 #define DP83825S_PHY_ID		0x2000a140
19 #define DP83825I_PHY_ID		0x2000a150
20 #define DP83825CM_PHY_ID	0x2000a160
21 #define DP83825CS_PHY_ID	0x2000a170
22 #define DP83826C_PHY_ID		0x2000a130
23 #define DP83826NC_PHY_ID	0x2000a110
25 #define MII_DP83822_CTRL_2	0x0a
26 #define MII_DP83822_PHYSTS	0x10
27 #define MII_DP83822_PHYSCR	0x11
28 #define MII_DP83822_MISR1	0x12
29 #define MII_DP83822_MISR2	0x13
30 #define MII_DP83822_FCSCR	0x14
31 #define MII_DP83822_RCSR	0x17
32 #define MII_DP83822_RESET_CTRL	0x1f
33 #define MII_DP83822_MLEDCR	0x25
34 #define MII_DP83822_LEDCFG1	0x460
35 #define MII_DP83822_IOCTRL1	0x462
36 #define MII_DP83822_IOCTRL2	0x463
37 #define MII_DP83822_GENCFG	0x465
38 #define MII_DP83822_SOR1	0x467
41 #define MII_DP83826_VOD_CFG1	0x30b
42 #define MII_DP83826_VOD_CFG2	0x30c
45 #define DP83822_SIG_DET_LOW	BIT(0)
56 #define DP83822_PHYSTS_LINK			BIT(0)
59 #define DP83822_PHYSCR_INT_OE		BIT(0) /* Interrupt Output Enable */
63 #define DP83822_RX_ERR_HF_INT_EN	BIT(0)
73 #define DP83822_JABBER_DET_INT_EN	BIT(0)
86 #define MII_DP83822_RXSOP1	0x04a5
87 #define	MII_DP83822_RXSOP2	0x04a6
88 #define	MII_DP83822_RXSOP3	0x04a7
91 #define	MII_DP83822_WOL_CFG	0x04a0
92 #define	MII_DP83822_WOL_STAT	0x04a1
93 #define	MII_DP83822_WOL_DA1	0x04a2
94 #define	MII_DP83822_WOL_DA2	0x04a3
95 #define	MII_DP83822_WOL_DA3	0x04a4
98 #define DP83822_WOL_MAGIC_EN	BIT(0)
113 #define DP83822_MLEDCR_ROUTE		GENMASK(1, 0)
122 #define DP83822_IOCTRL1_GPIO3_CTRL_LED3		BIT(0)
123 #define DP83822_IOCTRL1_GPIO1_CTRL		GENMASK(2, 0)
124 #define DP83822_IOCTRL1_GPIO1_CTRL_LED_1	BIT(0)
128 #define DP83822_IOCTRL2_GPIO2_CTRL		GENMASK(2, 0)
129 #define DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF	GENMASK(1, 0)
130 #define DP83822_IOCTRL2_GPIO2_CTRL_MLED		BIT(0)
132 #define DP83822_CLK_SRC_MAC_IF			0x0
133 #define DP83822_CLK_SRC_XI			0x1
134 #define DP83822_CLK_SRC_INT_REF			0x2
135 #define DP83822_CLK_SRC_RMII_MASTER_MODE_REF	0x4
136 #define DP83822_CLK_SRC_FREE_RUNNING		0x6
137 #define DP83822_CLK_SRC_RECOVERED		0x7
139 #define DP83822_LED_FN_LINK		0x0 /* Link established */
140 #define DP83822_LED_FN_RX_TX		0x1 /* Receive or Transmit activity */
141 #define DP83822_LED_FN_TX		0x2 /* Transmit activity */
142 #define DP83822_LED_FN_RX		0x3 /* Receive activity */
143 #define DP83822_LED_FN_COLLISION	0x4 /* Collision detected */
144 #define DP83822_LED_FN_LINK_100_BTX	0x5 /* 100 BTX link established */
145 #define DP83822_LED_FN_LINK_10_BT	0x6 /* 10BT link established */
146 #define DP83822_LED_FN_FULL_DUPLEX	0x7 /* Full duplex */
147 #define DP83822_LED_FN_LINK_RX_TX	0x8 /* Link established, blink for rx or tx activity */
148 #define DP83822_LED_FN_ACTIVE_STRETCH	0x9 /* Active Stretch Signal */
149 #define DP83822_LED_FN_MII_LINK		0xa /* MII LINK (100BT+FD) */
150 #define DP83822_LED_FN_LPI_MODE		0xb /* LPI Mode (EEE) */
151 #define DP83822_LED_FN_RX_TX_ERR	0xc /* TX/RX MII Error */
152 #define DP83822_LED_FN_LINK_LOST	0xd /* Link Lost */
153 #define DP83822_LED_FN_PRBS_ERR		0xe /* Blink for PRBS error */
156 #define DP83822_STRAP_MODE1	0
157 #define DP83822_STRAP_MODE2	BIT(0)
159 #define DP83822_STRAP_MODE4	GENMASK(1, 0)
171 #define DP83826_VOD_CFG2_PLUS_MDI_MASK		GENMASK(5, 0)
173 #define DP83826_CFG_DAC_MINUS_MDIX_3_TO_0	GENMASK(3, 0)
176 #define DP83826_CFG_DAC_MINUS_DEFAULT		0x30
177 #define DP83826_CFG_DAC_PLUS_DEFAULT		0x10
185 #define DP83822_LED_INDEX_LED_0		0
215 		/* MAC addresses start with byte 5, but stored in mac[0].  in dp83822_config_wol()
216 		 * 822 PHYs store bytes 4|5, 2|3, 0|1  in dp83822_config_wol()
219 			      (mac[1] << 8) | mac[0]);  in dp83822_config_wol()
235 				      (wol->sopass[1] << 8) | wol->sopass[0]);  in dp83822_config_wol()
283 	wol->wolopts = 0;  in dp83822_get_wol()
293 		wol->sopass[0] = (sopass_val & 0xff);  in dp83822_get_wol()
298 		wol->sopass[2] = (sopass_val & 0xff);  in dp83822_get_wol()
303 		wol->sopass[4] = (sopass_val & 0xff);  in dp83822_get_wol()
309 	/* WoL is not enabled so set wolopts to 0 */  in dp83822_get_wol()
311 		wol->wolopts = 0;  in dp83822_get_wol()
323 		if (misr_status < 0)  in dp83822_config_intr()
337 		if (err < 0)  in dp83822_config_intr()
341 		if (misr_status < 0)  in dp83822_config_intr()
355 		if (err < 0)  in dp83822_config_intr()
359 		if (physcr_status < 0)  in dp83822_config_intr()
365 		err = phy_write(phydev, MII_DP83822_MISR1, 0);  in dp83822_config_intr()
366 		if (err < 0)  in dp83822_config_intr()
369 		err = phy_write(phydev, MII_DP83822_MISR2, 0);  in dp83822_config_intr()
370 		if (err < 0)  in dp83822_config_intr()
374 		if (physcr_status < 0)  in dp83822_config_intr()
389 	 * the upper half (15:8), while the lower half (7:0) is used for  in dp83822_handle_interrupt()
396 	if (irq_status < 0) {  in dp83822_handle_interrupt()
400 	if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))  in dp83822_handle_interrupt()
404 	if (irq_status < 0) {  in dp83822_handle_interrupt()
408 	if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))  in dp83822_handle_interrupt()
432 			if (ctrl2 < 0)  in dp83822_read_status()
438 				if (ret < 0)  in dp83822_read_status()
448 	if (status < 0)  in dp83822_read_status()
461 	return 0;  in dp83822_read_status()
503 	return 0;  in dp83822_config_init_leds()
510 	int rgmii_delay = 0;  in dp83822_config_init()
513 	int err = 0;  in dp83822_config_init()
530 		rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,  in dp83822_config_init()
534 		if (rx_int_delay > 0)  in dp83822_config_init()
537 		tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,  in dp83822_config_init()
541 		if (tx_int_delay <= 0)  in dp83822_config_init()
565 		if (err < 0)  in dp83822_config_init()
587 		if (bmcr < 0)  in dp83822_config_init()
591 			err =  phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);  in dp83822_config_init()
592 			if (err < 0)  in dp83822_config_init()
606 		if (err < 0)  in dp83822_config_init()
627 		if (strcmp(of_val, "master") == 0) {  in dp8382x_config_rmii_mode()
630 		} else if (strcmp(of_val, "slave") == 0) {  in dp8382x_config_rmii_mode()
643 	return 0;  in dp8382x_config_rmii_mode()
716 	if (err < 0)  in dp83822_phy_reset()
732 		return 0;  in dp83822_of_init_leds()
736 		return 0;  in dp83822_of_init_leds()
775 	return 0;  in dp83822_of_init_leds()
796 		if (strcmp(of_val, "mac-if") == 0) {  in dp83822_of_init()
798 		} else if (strcmp(of_val, "xi") == 0) {  in dp83822_of_init()
800 		} else if (strcmp(of_val, "int-ref") == 0) {  in dp83822_of_init()
802 		} else if (strcmp(of_val, "rmii-master-mode-ref") == 0) {  in dp83822_of_init()
804 		} else if (strcmp(of_val, "free-running") == 0) {  in dp83822_of_init()
806 		} else if (strcmp(of_val, "recovered") == 0) {  in dp83822_of_init()
852 	return 0;  in dp83822_of_init()
867 	if (val < 0)  in dp83822_read_straps()
870 	phydev_dbg(phydev, "SOR1 strap register: 0x%04x\n", val);  in dp83822_read_straps()
884 	return 0;  in dp83822_read_straps()
898 	return 0;  in dp8382x_probe()
923 	return 0;  in dp83822_probe()
936 	return 0;  in dp83826_probe()
948 	return 0;  in dp83822_suspend()
962 	return 0;  in dp83822_resume()
997 	if (mode < 0)  in dp83822_led_hw_is_supported()
1000 	return 0;  in dp83822_led_hw_is_supported()
1009 	if (mode < 0)  in dp83822_led_hw_control_set()
1037 		if (val < 0)  in dp83822_led_hw_control_get()
1043 		if (val < 0)  in dp83822_led_hw_control_get()
1082 		*rules = 0;  in dp83822_led_hw_control_get()
1086 	return 0;  in dp83822_led_hw_control_get()
1153 	{ DP83822_PHY_ID, 0xfffffff0 },
1154 	{ DP83825I_PHY_ID, 0xfffffff0 },
1155 	{ DP83826C_PHY_ID, 0xfffffff0 },
1156 	{ DP83826NC_PHY_ID, 0xfffffff0 },
1157 	{ DP83825S_PHY_ID, 0xfffffff0 },
1158 	{ DP83825CM_PHY_ID, 0xfffffff0 },
1159 	{ DP83825CS_PHY_ID, 0xfffffff0 },