Lines Matching refs:phy_set_clr_bits

242 static int phy_set_clr_bits(struct phy_device *dev, int location,  in phy_set_clr_bits()  function
259 	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,  in bcm7xxx_28nm_ephy_01_afe_config_init()
274 	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,  in bcm7xxx_28nm_ephy_01_afe_config_init()
284 	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,  in bcm7xxx_28nm_ephy_01_afe_config_init()
291 	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,  in bcm7xxx_28nm_ephy_01_afe_config_init()
305 	ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST,  in bcm7xxx_28nm_ephy_apd_enable()
311 	ret = phy_set_clr_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,  in bcm7xxx_28nm_ephy_apd_enable()
317 	ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, 0,  in bcm7xxx_28nm_ephy_apd_enable()
330 	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,  in bcm7xxx_28nm_ephy_eee_enable()
376 	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,  in bcm7xxx_28nm_ephy_eee_enable()
709 	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,  in bcm7xxx_config_init()
724 	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, MII_BCM7XXX_SHD_MODE_2);  in bcm7xxx_config_init()