Lines Matching +full:0 +full:x0202
16 #define VEND1_GLOBAL_SC 0x0
20 #define VEND1_GLOBAL_FW_ID 0x0020
22 #define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
24 #define VEND1_GLOBAL_MAILBOX_INTERFACE1 0x0200
30 #define VEND1_GLOBAL_MAILBOX_INTERFACE2 0x0201
31 #define VEND1_GLOBAL_MAILBOX_INTERFACE3 0x0202
32 #define VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR_MASK GENMASK(15, 0)
34 #define VEND1_GLOBAL_MAILBOX_INTERFACE4 0x0203
38 #define VEND1_GLOBAL_MAILBOX_INTERFACE5 0x0204
39 #define VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA_MASK GENMASK(15, 0)
41 #define VEND1_GLOBAL_MAILBOX_INTERFACE6 0x0205
42 #define VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA_MASK GENMASK(15, 0)
46 #define VEND1_GLOBAL_CFG_10M 0x0310
47 #define VEND1_GLOBAL_CFG_100M 0x031b
48 #define VEND1_GLOBAL_CFG_1G 0x031c
49 #define VEND1_GLOBAL_CFG_2_5G 0x031d
50 #define VEND1_GLOBAL_CFG_5G 0x031e
51 #define VEND1_GLOBAL_CFG_10G 0x031f
53 #define VEND1_GLOBAL_CFG_SERDES_MODE GENMASK(2, 0)
54 #define VEND1_GLOBAL_CFG_SERDES_MODE_XFI 0
59 #define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
64 #define VEND1_GLOBAL_CONTROL2 0xc001
67 #define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL BIT(0)
69 #define VEND1_GLOBAL_LED_PROV 0xc430
79 #define VEND1_GLOBAL_LED_PROV_ACT_STRETCH GENMASK(0, 1)
87 #define VEND1_GLOBAL_LED_DRIVE 0xc438
91 #define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
92 #define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
93 #define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
94 #define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424
95 #define VEND1_THERMAL_STAT1 0xc820
96 #define VEND1_THERMAL_STAT2 0xc821
97 #define VEND1_THERMAL_STAT2_VALID BIT(0)
98 #define VEND1_GENERAL_STAT1 0xc830
104 #define VEND1_GLOBAL_GEN_STAT2 0xc831
107 #define VEND1_GLOBAL_RSVD_STAT1 0xc885
109 #define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
111 #define VEND1_GLOBAL_RSVD_STAT9 0xc88d
112 #define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
113 #define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
116 #define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292
117 #define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294
118 #define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297
119 #define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313
120 #define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315
121 #define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317
122 #define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318
123 #define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319
124 #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
125 #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
127 #define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
128 #define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
130 #define VEND1_GLOBAL_INT_STD_MASK 0xff00
141 #define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
143 #define VEND1_GLOBAL_INT_VEND_MASK 0xff01
151 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
186 static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; } in aqr_hwmon_probe()