4 #include <linux/pcs/pcs-xpcs.h>
6 #include "pcs-xpcs.h"
49 static int txgbe_write_pma(struct dw_xpcs *xpcs, int reg, u16 val)  in txgbe_write_pma()  argument
51 	return xpcs_write(xpcs, MDIO_MMD_PMAPMD, TXGBE_PMA_MMD + reg, val);  in txgbe_write_pma()
54 static int txgbe_modify_pma(struct dw_xpcs *xpcs, int reg, u16 mask, u16 set)  in txgbe_modify_pma()  argument
56 	return xpcs_modify(xpcs, MDIO_MMD_PMAPMD, TXGBE_PMA_MMD + reg, mask,  in txgbe_modify_pma()
60 static void txgbe_pma_config_10gbaser(struct dw_xpcs *xpcs)  in txgbe_pma_config_10gbaser()  argument
62 	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL0, 0x21);  in txgbe_pma_config_10gbaser()
63 	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL3, 0);  in txgbe_pma_config_10gbaser()
64 	txgbe_modify_pma(xpcs, TXGBE_TX_GENCTL1, TXGBE_TX_GENCTL1_VBOOST_LVL,  in txgbe_pma_config_10gbaser()
66 	txgbe_write_pma(xpcs, TXGBE_MISC_CTL0, TXGBE_MISC_CTL0_PLL |  in txgbe_pma_config_10gbaser()
68 	txgbe_write_pma(xpcs, TXGBE_VCO_CAL_LD0, 0x549);  in txgbe_pma_config_10gbaser()
69 	txgbe_write_pma(xpcs, TXGBE_VCO_CAL_REF0, 0x29);  in txgbe_pma_config_10gbaser()
70 	txgbe_write_pma(xpcs, TXGBE_TX_RATE_CTL, 0);  in txgbe_pma_config_10gbaser()
71 	txgbe_write_pma(xpcs, TXGBE_RX_RATE_CTL, 0);  in txgbe_pma_config_10gbaser()
72 	txgbe_write_pma(xpcs, TXGBE_TX_GEN_CTL2, TXGBE_TX_GEN_CTL2_TX0_WIDTH(3));  in txgbe_pma_config_10gbaser()
73 	txgbe_write_pma(xpcs, TXGBE_RX_GEN_CTL2, TXGBE_RX_GEN_CTL2_RX0_WIDTH(3));  in txgbe_pma_config_10gbaser()
74 	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL2, TXGBE_MPLLA_CTL2_DIV16P5_CLK_EN |  in txgbe_pma_config_10gbaser()
77 	txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL0, TXGBE_RX_EQ_CTL0_CTLE_POLE(2) |  in txgbe_pma_config_10gbaser()
79 	txgbe_modify_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, TXGBE_RX_EQ_ATTN_LVL0, 0);  in txgbe_pma_config_10gbaser()
80 	txgbe_write_pma(xpcs, TXGBE_DFE_TAP_CTL0, 0xBE);  in txgbe_pma_config_10gbaser()
81 	txgbe_modify_pma(xpcs, TXGBE_AFE_DFE_ENABLE,  in txgbe_pma_config_10gbaser()
83 	txgbe_modify_pma(xpcs, TXGBE_RX_EQ_CTL4, TXGBE_RX_EQ_CTL4_CONT_ADAPT0,  in txgbe_pma_config_10gbaser()
87 static void txgbe_pma_config_1g(struct dw_xpcs *xpcs)  in txgbe_pma_config_1g()  argument
89 	txgbe_modify_pma(xpcs, TXGBE_TX_GENCTL1,  in txgbe_pma_config_1g()
93 	txgbe_write_pma(xpcs, TXGBE_MISC_CTL0, TXGBE_MISC_CTL0_PLL |  in txgbe_pma_config_1g()
96 	txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL0, TXGBE_RX_EQ_CTL0_VGA1_GAIN(7) |  in txgbe_pma_config_1g()
98 	txgbe_modify_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, TXGBE_RX_EQ_ATTN_LVL0, 0);  in txgbe_pma_config_1g()
99 	txgbe_write_pma(xpcs, TXGBE_DFE_TAP_CTL0, 0);  in txgbe_pma_config_1g()
100 	txgbe_modify_pma(xpcs, TXGBE_RX_GEN_CTL3, TXGBE_RX_GEN_CTL3_LOS_TRSHLD0,  in txgbe_pma_config_1g()
103 	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL0, 0x20);  in txgbe_pma_config_1g()
104 	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL3, 0x46);  in txgbe_pma_config_1g()
105 	txgbe_write_pma(xpcs, TXGBE_VCO_CAL_LD0, 0x540);  in txgbe_pma_config_1g()
106 	txgbe_write_pma(xpcs, TXGBE_VCO_CAL_REF0, 0x2A);  in txgbe_pma_config_1g()
107 	txgbe_write_pma(xpcs, TXGBE_AFE_DFE_ENABLE, 0);  in txgbe_pma_config_1g()
108 	txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL4, TXGBE_RX_EQ_CTL4_CONT_OFF_CAN0);  in txgbe_pma_config_1g()
109 	txgbe_write_pma(xpcs, TXGBE_TX_RATE_CTL, TXGBE_TX_RATE_CTL_TX0_RATE(3));  in txgbe_pma_config_1g()
110 	txgbe_write_pma(xpcs, TXGBE_RX_RATE_CTL, TXGBE_RX_RATE_CTL_RX0_RATE(3));  in txgbe_pma_config_1g()
111 	txgbe_write_pma(xpcs, TXGBE_TX_GEN_CTL2, TXGBE_TX_GEN_CTL2_TX0_WIDTH(1));  in txgbe_pma_config_1g()
112 	txgbe_write_pma(xpcs, TXGBE_RX_GEN_CTL2, TXGBE_RX_GEN_CTL2_RX0_WIDTH(1));  in txgbe_pma_config_1g()
113 	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL2, TXGBE_MPLLA_CTL2_DIV10_CLK_EN);  in txgbe_pma_config_1g()
116 static int txgbe_pcs_poll_power_up(struct dw_xpcs *xpcs)  in txgbe_pcs_poll_power_up()  argument
120 	/* Wait xpcs power-up good */  in txgbe_pcs_poll_power_up()
124 				xpcs, DW_VR_XS_PCS_DIG_STS);  in txgbe_pcs_poll_power_up()
126 		dev_err(&xpcs->mdiodev->dev, "xpcs power-up timeout\n");  in txgbe_pcs_poll_power_up()
131 static int txgbe_pma_init_done(struct dw_xpcs *xpcs)  in txgbe_pma_init_done()  argument
135 	xpcs_write_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1, DW_VR_RST | DW_EN_VSMMD1);  in txgbe_pma_init_done()
140 				xpcs, DW_VR_XS_PCS_DIG_CTRL1);  in txgbe_pma_init_done()
142 		dev_err(&xpcs->mdiodev->dev, "xpcs pma initialization timeout\n");  in txgbe_pma_init_done()
147 static bool txgbe_xpcs_mode_quirk(struct dw_xpcs *xpcs)  in txgbe_xpcs_mode_quirk()  argument
152 	ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_CTRL2);  in txgbe_xpcs_mode_quirk()
155 	     xpcs->interface != PHY_INTERFACE_MODE_10GBASER) ||  in txgbe_xpcs_mode_quirk()
156 	    xpcs->interface == PHY_INTERFACE_MODE_SGMII)  in txgbe_xpcs_mode_quirk()
162 int txgbe_xpcs_switch_mode(struct dw_xpcs *xpcs, phy_interface_t interface)  in txgbe_xpcs_switch_mode()  argument
175 	if (xpcs->interface == interface && !txgbe_xpcs_mode_quirk(xpcs))  in txgbe_xpcs_switch_mode()
178 	xpcs->interface = interface;  in txgbe_xpcs_switch_mode()
180 	ret = txgbe_pcs_poll_power_up(xpcs);  in txgbe_xpcs_switch_mode()
185 		xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL2, MDIO_PCS_CTRL2_10GBR);  in txgbe_xpcs_switch_mode()
186 		xpcs_modify(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1,  in txgbe_xpcs_switch_mode()
188 		txgbe_pma_config_10gbaser(xpcs);  in txgbe_xpcs_switch_mode()
190 		xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL2, MDIO_PCS_CTRL2_10GBX);  in txgbe_xpcs_switch_mode()
191 		xpcs_write(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1, 0);  in txgbe_xpcs_switch_mode()
192 		xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL1, 0);  in txgbe_xpcs_switch_mode()
193 		txgbe_pma_config_1g(xpcs);  in txgbe_xpcs_switch_mode()
196 	return txgbe_pma_init_done(xpcs);  in txgbe_xpcs_switch_mode()