Lines Matching +full:switch +full:- +full:x +full:- +full:sgmii
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2018-2019 MediaTek Inc.
3 /* A library for MediaTek SGMII circuit
13 #include <linux/pcs/pcs-mtk-lynxi.h>
17 /* SGMII subsystem config registers */
50 /* Register to reset SGMII design */
54 /* Register to set SGMII speed, ANA RG_ Control Signals III */
68 /* struct mtk_pcs_lynxi - This structure holds each sgmii regmap andassociated
71 * SGMII modes
94 switch (interface) { in mtk_pcs_lynxi_inband_caps()
115 regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &bm); in mtk_pcs_lynxi_get_state()
116 regmap_read(mpcs->regmap, SGMSYS_PCS_ADVERTISE, &adv); in mtk_pcs_lynxi_get_state()
138 /* Clearing IF_MODE_BIT0 switches the PCS to BASE-X mode, and in mtk_pcs_lynxi_config()
158 if (mpcs->interface != interface) { in mtk_pcs_lynxi_config()
164 regmap_set_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, in mtk_pcs_lynxi_config()
167 /* Reset SGMII PCS state */ in mtk_pcs_lynxi_config()
168 regmap_set_bits(mpcs->regmap, SGMSYS_RESERVED_0, in mtk_pcs_lynxi_config()
171 if (mpcs->flags & MTK_SGMII_FLAG_PN_SWAP) in mtk_pcs_lynxi_config()
172 regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL, in mtk_pcs_lynxi_config()
182 regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3, in mtk_pcs_lynxi_config()
186 regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER, in mtk_pcs_lynxi_config()
189 mpcs->interface = interface; in mtk_pcs_lynxi_config()
194 regmap_update_bits_check(mpcs->regmap, SGMSYS_PCS_ADVERTISE, in mtk_pcs_lynxi_config()
198 regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE, in mtk_pcs_lynxi_config()
203 regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1, in mtk_pcs_lynxi_config()
209 * prevents SGMII from working. The SGMII still shows link but no traffic in mtk_pcs_lynxi_config()
211 * taken from a good working state of the SGMII interface. in mtk_pcs_lynxi_config()
216 regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0); in mtk_pcs_lynxi_config()
225 regmap_set_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1, BMCR_ANRESTART); in mtk_pcs_lynxi_restart_an()
248 regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE, in mtk_pcs_lynxi_link_up()
258 mpcs->interface = PHY_INTERFACE_MODE_NA; in mtk_pcs_lynxi_disable()
283 dev_err(dev, "unknown PCS device id %08x\n", id); in mtk_pcs_lynxi_create()
293 dev_err(dev, "unknown PCS device version %04x\n", ver); in mtk_pcs_lynxi_create()
297 dev_dbg(dev, "MediaTek LynxI SGMII PCS (id 0x%08x, ver 0x%04x)\n", id, in mtk_pcs_lynxi_create()
304 mpcs->ana_rgc3 = ana_rgc3; in mtk_pcs_lynxi_create()
305 mpcs->regmap = regmap; in mtk_pcs_lynxi_create()
306 mpcs->flags = flags; in mtk_pcs_lynxi_create()
307 mpcs->pcs.ops = &mtk_pcs_lynxi_ops; in mtk_pcs_lynxi_create()
308 mpcs->pcs.neg_mode = true; in mtk_pcs_lynxi_create()
309 mpcs->pcs.poll = true; in mtk_pcs_lynxi_create()
310 mpcs->interface = PHY_INTERFACE_MODE_NA; in mtk_pcs_lynxi_create()
312 __set_bit(PHY_INTERFACE_MODE_SGMII, mpcs->pcs.supported_interfaces); in mtk_pcs_lynxi_create()
313 __set_bit(PHY_INTERFACE_MODE_1000BASEX, mpcs->pcs.supported_interfaces); in mtk_pcs_lynxi_create()
314 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mpcs->pcs.supported_interfaces); in mtk_pcs_lynxi_create()
316 return &mpcs->pcs; in mtk_pcs_lynxi_create()
329 MODULE_DESCRIPTION("MediaTek SGMII library for LynxI");