Lines Matching +full:9 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
13 /* Bit 0 reserved */
14 [GSI_SNOC_BYPASS_DIS] = BIT(1),
15 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
16 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
17 [IPA_DCMP_FAST_CLK_EN] = BIT(4),
18 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
19 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
21 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
22 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
23 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
24 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
25 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
26 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
27 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
28 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
29 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
31 /* Bits 21-31 reserved */
37 [CLKON_RX] = BIT(0),
38 [CLKON_PROC] = BIT(1),
39 [TX_WRAPPER] = BIT(2),
40 [CLKON_MISC] = BIT(3),
41 [RAM_ARB] = BIT(4),
42 [FTCH_HPS] = BIT(5),
43 [FTCH_DPS] = BIT(6),
44 [CLKON_HPS] = BIT(7),
45 [CLKON_DPS] = BIT(8),
46 [RX_HPS_CMDQS] = BIT(9),
47 [HPS_DPS_CMDQS] = BIT(10),
48 [DPS_TX_CMDQS] = BIT(11),
49 [RSRC_MNGR] = BIT(12),
50 [CTX_HANDLER] = BIT(13),
51 [ACK_MNGR] = BIT(14),
52 [D_DCPH] = BIT(15),
53 [H_DCPH] = BIT(16),
54 /* Bit 17 reserved */
55 [NTF_TX_CMDQS] = BIT(18),
56 [CLKON_TX_0] = BIT(19),
57 [CLKON_TX_1] = BIT(20),
58 [CLKON_FNR] = BIT(21),
59 [QSB2AXI_CMDQ_L] = BIT(22),
60 [AGGR_WRAPPER] = BIT(23),
61 [RAM_SLAVEWAY] = BIT(24),
62 [CLKON_QMB] = BIT(25),
63 [WEIGHT_ARB] = BIT(26),
64 [GSI_IF] = BIT(27),
65 [CLKON_GLOBAL] = BIT(28),
66 [GLOBAL_2X_CLK] = BIT(29),
67 /* Bits 30-31 reserved */
73 [ROUTE_DIS] = BIT(0),
75 [ROUTE_DEF_HDR_TABLE] = BIT(6),
78 /* Bits 22-23 reserved */
79 [ROUTE_DEF_RETAIN_HDR] = BIT(24),
80 /* Bits 25-31 reserved */
95 /* Bits 8-31 reserved */
103 /* Bits 8-15 reserved */
111 [IPV6_ROUTER_HASH] = BIT(0),
112 /* Bits 1-3 reserved */
113 [IPV6_FILTER_HASH] = BIT(4),
114 /* Bits 5-7 reserved */
115 [IPV4_ROUTER_HASH] = BIT(8),
116 /* Bits 9-11 reserved */
117 [IPV4_FILTER_HASH] = BIT(12),
118 /* Bits 13-31 reserved */
124 [IPV6_ROUTER_HASH] = BIT(0),
125 /* Bits 1-3 reserved */
126 [IPV6_FILTER_HASH] = BIT(4),
127 /* Bits 5-7 reserved */
128 [IPV4_ROUTER_HASH] = BIT(8),
129 /* Bits 9-11 reserved */
130 [IPV4_FILTER_HASH] = BIT(12),
131 /* Bits 13-31 reserved */
136 /* Valid bits defined by ipa->available */
143 /* Bits 17-31 reserved */
149 /* Valid bits defined by ipa->available */
153 /* Bits 0-3 reserved */
155 /* Bits 9-31 reserved */
161 /* Bits 0-1 reserved */
163 [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),
164 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
165 [DMAW_MAX_BEATS_256_DIS] = BIT(11),
166 [PA_MASK_EN] = BIT(12),
168 /* Bit 17 reserved */
169 [SSPND_PA_NO_START_STATE] = BIT(18),
170 [SSPND_PA_NO_BQ_STATE] = BIT(19),
171 /* Bits 20-31 reserved */
178 /* Bits 4-7 reserved */
180 /* Bits 13-15 reserved */
182 /* Bits 21-23 reserved */
184 /* Bits 28-31 reserved */
191 [CONST_NON_IDLE_ENABLE] = BIT(16),
192 /* Bits 17-31 reserved */
199 /* Bits 6-7 reserved */
201 /* Bits 14-15 reserved */
203 /* Bits 22-23 reserved */
205 /* Bits 30-31 reserved */
213 /* Bits 6-7 reserved */
215 /* Bits 14-15 reserved */
217 /* Bits 22-23 reserved */
219 /* Bits 30-31 reserved */
227 /* Bits 6-7 reserved */
229 /* Bits 14-15 reserved */
231 /* Bits 22-23 reserved */
233 /* Bits 30-31 reserved */
241 /* Bits 6-7 reserved */
243 /* Bits 14-15 reserved */
245 /* Bits 22-23 reserved */
247 /* Bits 30-31 reserved */
254 [FRAG_OFFLOAD_EN] = BIT(0),
257 /* Bit 7 reserved */
258 [CS_GEN_QMB_MASTER_SEL] = BIT(8),
259 /* Bits 9-31 reserved */
266 /* Bits 2-31 reserved */
273 [HDR_OFST_METADATA_VALID] = BIT(6),
276 [HDR_OFST_PKT_SIZE_VALID] = BIT(19),
278 [HDR_A5_MUX] = BIT(26),
279 [HDR_LEN_INC_DEAGG_HDR] = BIT(27),
280 [HDR_METADATA_REG_VALID] = BIT(28),
281 /* Bits 29-31 reserved */
287 [HDR_ENDIANNESS] = BIT(0),
288 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
289 [HDR_TOTAL_LEN_OR_PAD] = BIT(2),
290 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
291 [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),
293 /* Bits 14-31 reserved */
303 /* Bit 3 reserved */
305 /* Bits 9-11 reserved */
307 [PIPE_REPLICATION_EN] = BIT(28),
308 [PAD_EN] = BIT(29),
309 [HDR_FTCH_DISABLE] = BIT(30),
310 /* Bit 31 reserved */
318 [BYTE_LIMIT] = GENMASK(9, 5),
321 [SW_EOF_ACTIVE] = BIT(21),
322 [FORCE_CLOSE] = BIT(22),
323 /* Bit 23 reserved */
324 [HARD_BYTE_LIMIT_EN] = BIT(24),
325 /* Bits 25-31 reserved */
331 [HOL_BLOCK_EN] = BIT(0),
332 /* Bits 1-31 reserved */
340 /* Bits 5-7 reserved */
342 /* Bits 9-31 reserved */
350 [SYSPIPE_ERR_DETECTION] = BIT(6),
351 [PACKET_OFFSET_VALID] = BIT(7),
353 [IGNORE_MIN_PKT_ERR] = BIT(14),
354 /* Bit 15 reserved */
361 [ENDP_RSRC_GRP] = BIT(0),
362 /* Bits 1-31 reserved */
370 /* Bits 16-31 reserved */
376 [STATUS_EN] = BIT(0),
378 /* Bits 6-7 reserved */
379 [STATUS_LOCATION] = BIT(8),
380 [STATUS_PKT_SUPPRESS] = BIT(9),
381 /* Bits 10-31 reserved */
396 [UC_INTR] = BIT(0),
397 /* Bits 1-31 reserved */
402 /* Valid bits defined by ipa->available */
406 /* Valid bits defined by ipa->available */
410 /* Valid bits defined by ipa->available */