Lines Matching +full:sync +full:- +full:write
1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Write Register 0 */
37 /* Write Register 1 */
52 /* Write Register #2 (Interrupt Vector) */
54 /* Write Register 3 */
57 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
67 /* Write Register 4 */
72 #define SYNC_ENAB 0 /* Sync Modes Enable */
77 #define MONSYNC 0 /* 8 Bit Sync character */
78 #define BISYNC 0x10 /* 16 bit sync character */
79 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
80 #define EXTSYNC 0x30 /* External Sync Mode */
87 /* Write Register 5 */
91 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
100 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
102 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
104 /* Write Register 8 (transmit buffer) */
106 /* Write Register 9 (Master interrupt control) */
112 #define NORESET 0 /* No reset on write to R9 */
117 /* Write Register 10 (misc control bits) */
118 #define BIT6 1 /* 6 bit/8bit sync */
129 /* Write Register 11 (Clock Mode control) */
145 /* Write Register 12 (lower byte of baud rate generator time constant) */
147 /* Write Register 13 (upper byte of baud rate generator time constant) */
149 /* Write Register 14 (Misc control bits) */
163 /* Write Register 15 (external/status interrupt control) */
166 #define SYNCIE 0x10 /* Sync/hunt IE */
177 #define SYNC_HUNT 0x10 /* Sync/hunt */
199 /* Read Register 2 (channel b only) - Interrupt vector */
225 /* Write Register 7' (SDLC/HDLC Programmable Enhancements) */
236 /* Write Register 15 (external/status interrupt control) */