Lines Matching +full:rx +full:- +full:sync +full:- +full:clock
1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
43 #define RxINT_DISAB 0 /* Rx Int Disable */
44 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
45 #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
56 #define RxENABLE 0x1 /* Rx Enable */
57 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
59 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
62 #define Rx5 0x0 /* Rx 5 Bits/Character */
63 #define Rx7 0x40 /* Rx 7 Bits/Character */
64 #define Rx6 0x80 /* Rx 6 Bits/Character */
65 #define Rx8 0xc0 /* Rx 8 Bits/Character */
72 #define SYNC_ENAB 0 /* Sync Modes Enable */
77 #define MONSYNC 0 /* 8 Bit Sync character */
78 #define BISYNC 0x10 /* 16 bit sync character */
79 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
80 #define EXTSYNC 0x30 /* External Sync Mode */
82 #define X1CLK 0x0 /* x1 clock mode */
83 #define X16CLK 0x40 /* x16 clock mode */
84 #define X32CLK 0x80 /* x32 clock mode */
85 #define X64CLK 0xC0 /* x64 clock mode */
91 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
100 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
102 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
118 #define BIT6 1 /* 6 bit/8bit sync */
129 /* Write Register 11 (Clock Mode control) */
131 #define TRxCTC 1 /* TRxC = Transmit clock */
135 #define TCRTxCP 0 /* Transmit clock = RTxC pin */
136 #define TCTRxCP 8 /* Transmit clock = TRxC pin */
137 #define TCBR 0x10 /* Transmit clock = BR Generator output */
138 #define TCDPLL 0x18 /* Transmit clock = DPLL output */
139 #define RCRTxCP 0 /* Receive clock = RTxC pin */
140 #define RCTRxCP 0x20 /* Receive clock = TRxC pin */
141 #define RCBR 0x40 /* Receive clock = BR Generator output */
142 #define RCDPLL 0x60 /* Receive clock = DPLL output */
156 #define RMC 0x40 /* Reset missing clock */
166 #define SYNCIE 0x10 /* Sync/hunt IE */
173 #define Rx_CH_AV 0x1 /* Rx Character Available */
177 #define SYNC_HUNT 0x10 /* Sync/hunt */
184 /* Residue Data for 8 Rx bits/char programmed */
193 /* Special Rx Condition Interrupts */
195 #define Rx_OVR 0x20 /* Rx Overrun Error */
199 /* Read Register 2 (channel b only) - Interrupt vector */
204 #define CHBRxIP 0x4 /* Channel B Rx IP */
207 #define CHARxIP 0x20 /* Channel A Rx IP */
215 #define CLK1MIS 0x80 /* One clock missing */
230 #define RXFIFOH 0x08 /* Z85230: Int on RX FIFO half full */