Lines Matching +full:2 +full:w
42 #define FS_EI (1<<2)
65 #define FRM_IMPA (2)
92 unsigned int rx_erfbb :2 ; /* received frame byte boundary */
93 unsigned int rx_reserv2:2 ; /* reserved */
115 unsigned int rx_erfbb :2 ; /* received frame byte boundary */
116 unsigned int rx_reserv2:2 ; /* reserved */
145 #define RD_FRM_IMPA (unsigned long)(2<<20)
153 #define TXP1 2
166 unsigned int tx_rpxm :2 ; /* byte offset */
167 unsigned int tx_pat1 :2 ; /* must be TXP1 */
171 unsigned int tx_pat1 :2 ; /* must be TXP1 */
172 unsigned int tx_rpxm :2 ; /* byte offset */
227 u_char tq_pad[2] ;
235 * FORMAC+ read/write (r/w) registers
238 #define FM_CMDREG2 0x01 /* write command reg 2 instruction */
241 #define FM_ST2U 0x02 /* read upper 16-bit of status reg 2 */
242 #define FM_ST2L 0x03 /* read lower 16-bit of status reg 2 */
243 #define FM_IMSK1U 0x04 /* r/w upper 16-bit of IMSK 1 */
244 #define FM_IMSK1L 0x05 /* r/w lower 16-bit of IMSK 1 */
245 #define FM_IMSK2U 0x06 /* r/w upper 16-bit of IMSK 2 */
246 #define FM_IMSK2L 0x07 /* r/w lower 16-bit of IMSK 2 */
247 #define FM_SAID 0x08 /* r/w short addr.-individual */
248 #define FM_LAIM 0x09 /* r/w long addr.-ind. (MSW of LAID) */
249 #define FM_LAIC 0x0a /* r/w long addr.-ind. (middle)*/
250 #define FM_LAIL 0x0b /* r/w long addr.-ind. (LSW) */
251 #define FM_SAGP 0x0c /* r/w short address-group */
252 #define FM_LAGM 0x0d /* r/w long addr.-gr. (MSW of LAGP) */
253 #define FM_LAGC 0x0e /* r/w long addr.-gr. (middle) */
254 #define FM_LAGL 0x0f /* r/w long addr.-gr. (LSW) */
255 #define FM_MDREG1 0x10 /* r/w 16-bit mode reg 1 */
259 #define FM_TMAX 0x14 /* r/w 16-bit TMAX reg */
262 #define FM_TRT 0x16 /* r/w upper 16-bit of TRT timer */
263 #define FM_THT 0x17 /* r/w upper 16-bit of THT timer */
266 /* F E D C B A 9 8 7 6 5 4 3 2 1 0
268 #define FM_TREQ0 0x1a /* r/w 16-bit TREQ0 reg (LSW of TRT) */
269 #define FM_TREQ1 0x1b /* r/w 16-bit TREQ1 reg (MSW of TRT) */
270 #define FM_PRI0 0x1c /* r/w priority r. for asyn.-queue 0 */
271 #define FM_PRI1 0x1d /* r/w priority r. for asyn.-queue 1 */
272 #define FM_PRI2 0x1e /* r/w priority r. for asyn.-queue 2 */
273 #define FM_TSYNC 0x1f /* r/w 16-bit of the TSYNC register */
274 #define FM_MDREG2 0x20 /* r/w 16-bit mode reg 2 */
275 #define FM_FRMTHR 0x21 /* r/w the frame threshold register */
276 #define FM_EACB 0x22 /* r/w end addr of claim/beacon area */
277 #define FM_EARV 0x23 /* r/w end addr of receive queue */
281 #define FM_EAS 0x24 /* r/w end addr of synchr. queue */
282 #define FM_EAA0 0x25 /* r/w end addr of asyn. queue 0 */
283 #define FM_EAA1 0x26 /* r/w end addr of asyn. queue 1 */
284 #define FM_EAA2 0x27 /* r/w end addr of asyn. queue 2 */
285 #define FM_SACL 0x28 /* r/w start addr of claim frame */
286 #define FM_SABC 0x29 /* r/w start addr of beacon frame */
287 #define FM_WPXSF 0x2a /* r/w the write ptr. for special fr.*/
288 #define FM_RPXSF 0x2b /* r/w the read ptr. for special fr. */
289 #define FM_RPR 0x2d /* r/w the read ptr. for receive qu. */
290 #define FM_WPR 0x2e /* r/w the write ptr. for receive qu.*/
291 #define FM_SWPR 0x2f /* r/w the shadow wr.-ptr. for rec.q.*/
297 #define FM_WPXS 0x30 /* r/w the write ptr. for synchr. qu.*/
298 #define FM_WPXA0 0x31 /* r/w the write ptr. for asyn. qu.0 */
299 #define FM_WPXA1 0x32 /* r/w the write ptr. for asyn. qu.1 */
300 #define FM_WPXA2 0x33 /* r/w the write ptr. for asyn. qu.2 */
301 #define FM_SWPXS 0x34 /* r/w the shadow wr.-ptr. for syn.q.*/
302 #define FM_SWPXA0 0x35 /* r/w the shad. wr.-ptr. for asyn.q0*/
303 #define FM_SWPXA1 0x36 /* r/w the shad. wr.-ptr. for asyn.q1*/
304 #define FM_SWPXA2 0x37 /* r/w the shad. wr.-ptr. for asyn.q2*/
305 #define FM_RPXS 0x38 /* r/w the read ptr. for synchr. qu. */
306 #define FM_RPXA0 0x39 /* r/w the read ptr. for asyn. qu. 0 */
307 #define FM_RPXA1 0x3a /* r/w the read ptr. for asyn. qu. 1 */
308 #define FM_RPXA2 0x3b /* r/w the read ptr. for asyn. qu. 2 */
309 #define FM_MARR 0x3c /* r/w the memory read addr register */
310 #define FM_MARW 0x3d /* r/w the memory write addr register*/
311 #define FM_MDRU 0x3e /* r/w upper 16-bit of mem. data reg */
312 #define FM_MDRL 0x3f /* r/w lower 16-bit of mem. data reg */
315 #define FM_TMSYNC 0x40 /* r/w upper 16 bits of TMSYNC timer */
316 #define FM_FCNTR 0x41 /* r/w the 16-bit frame counter */
317 #define FM_LCNTR 0x42 /* r/w the 16-bit lost counter */
318 #define FM_ECNTR 0x43 /* r/w the 16-bit error counter */
322 #define FM_FRSELREG 0x45 /* r/w Frame Selection Register */
324 /* Supernet 3: extensions for 2. receive queue etc. */
325 #define FM_MDREG3 0x60 /* r/w Mode Register 3 */
328 #define FM_IMSK3U 0x63 /* r/w upper 16-bit of IMSK reg 3 */
329 #define FM_IMSK3L 0x64 /* r/w lower 16-bit of IMSK reg 3 */
331 #define FM_IMR 0x66 /* r/w Interrupt mask register */
333 #define FM_RPR2 0x68 /* r/w the read ptr. for rec. qu. 2 */
334 #define FM_WPR2 0x69 /* r/w the write ptr. for rec. qu. 2 */
335 #define FM_SWPR2 0x6a /* r/w the shadow wptr. for rec. q. 2 */
336 #define FM_EARV2 0x6b /* r/w end addr of rec. qu. 2 */
337 #define FM_UNLCKDLY 0x6c /* r/w Auto Unlock Delay register */
341 #define FM_LTDPA1 0x79 /* r/w Last Trans desc ptr for A1 qu. */
345 #define FM_AFCMD 0xb0 /* r/w Address Filter Command Reg */
346 #define FM_AFSTAT 0xb2 /* r/w Address Filter Status Reg */
347 #define FM_AFBIST 0xb4 /* r/w Address Filter BIST signature */
348 #define FM_AFCOMP2 0xb6 /* r/w Address Filter Comparand 2 */
349 #define FM_AFCOMP1 0xb8 /* r/w Address Filter Comparand 1 */
350 #define FM_AFCOMP0 0xba /* r/w Address Filter Comparand 0 */
351 #define FM_AFMASK2 0xbc /* r/w Address Filter Mask 2 */
352 #define FM_AFMASK1 0xbe /* r/w Address Filter Mask 1 */
353 #define FM_AFMASK0 0xc0 /* r/w Address Filter Mask 0 */
354 #define FM_AFPERS 0xc2 /* r/w Address Filter Personality Reg */
357 #define FM_ORBIST 0xd0 /* r/w Orion BIST signature */
358 #define FM_ORSTAT 0xd2 /* r/w Orion Status Register */
380 #define FM_MRNNSAFNMA (2<<8) /* rec. non-NSA frames DA=MA&&SA!=MA */
392 #define FM_MONLINESP (2<<12) /* on-line special */
405 * Mode Register 2 (MDREG2)
428 #define FM_STEFRMA2 0x0008 /* transmit end of frame: asyn. qu.2 */
445 #define FM_STXABRA2 0x4000 /* asynchr. queue 2 transmit-abort */
455 #define FM_SQLCKA2 0x0008 /* queue lock for asynchr. queue 2 */
463 #define FM_STXINFLA2 0x0080 /* transmit instruction full: asyn.2 */
473 #define FM_STBURA2 0x8000 /* transmit buffer underrun: asyn.2 */
477 * Status Register 2, Upper 16 Bits (ST2U)
499 * Status Register 2, Lower 16 Bits (ST2L)
525 #define FM_SRQUNLCK2 0x0002 /* receive queue unlocked queue 2 */
527 #define FM_SRPERRQ2 0x0008 /* receive parity error rx queue 2 */
529 #define FM_SRCVOVR2 0x0800 /* receive FIFO overfull rx queue 2 */
530 #define FM_SRBFL2 0x1000 /* receive buffer full rx queue 2 */
531 #define FM_SRABT2 0x2000 /* receive abort rx queue 2 */
532 #define FM_SRBMT2 0x4000 /* receive buf empty rx queue 2 */
533 #define FM_SRCOMP2 0x8000 /* receive comp rx queue 2 */
552 #define FM_SNPPND 0x0008 /* r/w from buffer mem. is pending */
585 #define FM_RCV1_SMT (2<<0) /* rec all SMT frames */
593 #define FM_RECV2 0x00f0 /* options for receive queue 2 */
596 #define FM_RCV2_SMT (2<<4) /* rec all SMT frames */
614 #define FM_IREAD_CAM (2<<0) /* Read CAM */
674 #define FM_ICLLA2 0x18 /* clear asynchronous queue 2 lock */
677 #define FM_ICLLR2 0x21 /* SN3: clear receive queue 2 lock */
683 * instruction set for command register 2 (NPADDR6-0 = 0x01)
691 #define FM_ITRA2 0x08 /* transmit asynchronous queue 2 */
706 * PLC read/write (r/w) registers
708 #define PL_CNTRL_A 0x00 /* control register A (r/w) */
709 #define PL_CNTRL_B 0x01 /* control register B (r/w) */
710 #define PL_INTR_MASK 0x02 /* interrupt mask (r/w) */
711 #define PL_XMIT_VECTOR 0x03 /* transmit vector register (r/w) */
712 #define PL_VECTOR_LEN 0x04 /* transmit vector length (r/w) */
713 #define PL_LE_THRESHOLD 0x05 /* link error event threshold (r/w) */
714 #define PL_C_MIN 0x06 /* minimum connect state time (r/w) */
715 #define PL_TL_MIN 0x07 /* min. line state transmit t. (r/w) */
716 #define PL_TB_MIN 0x08 /* minimum break time (r/w) */
717 #define PL_T_OUT 0x09 /* signal timeout (r/w) */
718 #define PL_CNTRL_C 0x0a /* control register C (r/w) */
719 #define PL_LC_LENGTH 0x0b /* link confidence test time (r/w) */
720 #define PL_T_SCRUB 0x0c /* scrub time = MAC TVX (r/w) */
721 #define PL_NS_MAX 0x0d /* max. noise time before break (r/w)*/
745 #define QELM_XBAR_W 0x80 /* Crossbar Control ELM W */
753 #define QELM_CTR_W 0x88 /* Counter W */
791 #define PL_PCM_TRACE (2) /* goes to the TRACE state */
801 #define PL_TIDLE (2<<5) /* PCM asserts transmit idle */
809 #define PL_M_HALT (2<<8) /* transmit HALT line state */
819 #define PL_I_HALT (2<<11) /* Interrupt on HALT line state */
834 #define PL_C_FOTOFF_CTRL (3<<2) /* FOTOFF timer control */
835 #define PL_C_FOTOFF_TIM (0<<2) /* FOTOFF use timer for (de)-assert */
836 #define PL_C_FOTOFF_INA (2<<2) /* FOTOFF forced inactive */
837 #define PL_C_FOTOFF_ACT (3<<2) /* FOTOFF forced active */
845 #define PL_C_FOTOFF_50 (2<<8) /* 50uS */
850 #define PL_C_SDON_252 (2<<10) /* 2.52 uS */
855 #define PL_C_SOFF_252 (2<<12) /* 2.52 uS */
886 #define PL_L_UND (2<<5) /* undefined */
896 #define PL_P_HLS (2<<8) /* halt line state */
909 #define PL_B_TPC (2) /* TPC timer expired after T_OUT */
923 #define PL_PC2 (2<<7) /* TRACE - to localize stuck Beacon*/
928 #define PL_PC7 (7<<7) /* VERIFY - 2. - " - (3. ACTIVE) */
938 #define PL_CI_RSCR (2<<12) /* REMOVE_SCRUB */
944 #define PL_RF_HALT1 (2<<14) /* HALT1 */
968 #define PL_NP_ERR 0x8000 /* NP has requested to r/w an inv. r.*/
984 #define QELM_XOUT_W 0x0004 /* Output to: ELM W */
996 #define QELM_COUNT_W (1<<4) /* Counter W Interrupt */
998 #define QELM_ELM_Y (1<<2) /* ELM Y Interrupt */
1000 #define QELM_ELM_W (1<<0) /* ELM W Interrupt */
1005 #define TP_C_MIN 0xff9c /* 2 ms */
1037 #define RQ_SFW 2 /* special frame write */
1042 #define RQ_WA2 7 /* write requ.: asynchronous queue 2 */
1049 * AMD chips use BCLK as unit. 1 BCKL == 2 symbols