Lines Matching +full:0 +full:xe2000
94 #define MANFID_COMPAQ 0x0138
95 #define MANFID_COMPAQ2 0x0183 /* is this correct? */
108 #define XIRCREG_CR 0 /* Command register (wr) */
110 TransmitPacket = 0x01,
111 SoftReset = 0x02,
112 EnableIntr = 0x04,
113 ForceIntr = 0x08,
114 ClearTxFIFO = 0x10,
115 ClearRxOvrun = 0x20,
116 RestartTx = 0x40
118 #define XIRCREG_ESR 0 /* Ethernet status register (rd) */
120 FullPktRcvd = 0x01, /* full packet in receive buffer */
121 PktRejected = 0x04, /* a packet has been rejected */
122 TxPktPend = 0x08, /* TX Packet Pending */
123 IncorPolarity = 0x10,
124 MediaSelect = 0x20 /* set if TP, clear if AUI */
130 TxBufOvr = 0x01, /* TX Buffer Overflow */
131 PktTxed = 0x02, /* Packet Transmitted */
132 MACIntr = 0x04, /* MAC Interrupt occurred */
133 TxResGrant = 0x08, /* Tx Reservation Granted */
134 RxFullPkt = 0x20, /* Rx Full Packet */
135 RxPktRej = 0x40, /* Rx Packet Rejected */
136 ForcedIntr= 0x80 /* Forced Interrupt */
140 #define XIRCREG0_TSO 8 /* Transmit Space Open Register (on page 0)*/
141 #define XIRCREG0_TRS 10 /* Transmit reservation Size Register (page 0)*/
142 #define XIRCREG0_DO 12 /* Data Offset Register (page 0) (wr) */
143 #define XIRCREG0_RSR 12 /* Receive Status Register (page 0) (rd) */
145 PhyPkt = 0x01, /* set:physical packet, clear: multicast packet */
146 BrdcstPkt = 0x02, /* set if it is a broadcast packet */
147 PktTooLong = 0x04, /* set if packet length > 1518 */
148 AlignErr = 0x10, /* incorrect CRC and last octet not complete */
149 CRCErr = 0x20, /* incorrect CRC and last octet is complete */
150 PktRxOk = 0x80 /* received ok */
156 FullDuplex = 0x04, /* enable full duplex mode */
157 LongTPMode = 0x08, /* adjust for longer lengths of TP cable */
158 DisablePolCor = 0x10,/* disable auto polarity correction */
159 DisableLinkPulse = 0x20, /* disable link pulse generation */
160 DisableAutoTx = 0x40, /* disable auto-transmit */
164 /* values for the leds: Bits 2-0 for led 1
165 * 0 disabled Bits 5-3 for led 2
176 #define XIRCREG4_GPR0 8 /* General Purpose Register 0 */
185 Transmit = 0x01,
186 EnableRecv = 0x04,
187 DisableRecv = 0x08,
188 Abort = 0x10,
189 Online = 0x20,
190 IntrAck = 0x40,
191 Offline = 0x80
195 #define XIRCREG40_TXST0 11 /* Transmit Status Register 0 */
198 #define XIRCREG40_TMASK0 14 /* Transmit Mask Register 0 */
199 #define XIRCREG40_TMASK1 15 /* Transmit Mask Register 0 */
200 #define XIRCREG42_SWC0 8 /* Software Configuration 0 */
203 #define XIRCREG44_TDR0 8 /* Time Domain Reflectometry 0 */
205 #define XIRCREG44_RXBC_LO 10 /* Rx Byte Count 0 (rd) */
213 #define XIR_UNKNOWN 0 /* unknown: not supported */
235 #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
237 INT_MODULE_PARM(if_port, 0);
238 INT_MODULE_PARM(full_duplex, 0);
240 INT_MODULE_PARM(lockup_hack, 0); /* anti lockup hack */
275 int silicon; /* silicon revision. 0=old CE2, 1=Scipper, 4=Mohawk */
314 #if 0 /* reading regs may change system status */
324 for (i = 0; i < 8; i++)
327 for (page = 0; page <= 8; page++) {
334 for (page=0x40 ; page <= 0x5f; page++) {
335 if (page == 0x43 || (page >= 0x46 && page <= 0x4f) ||
336 (page >= 0x51 && page <=0x5e))
346 #endif /* 0 */
356 PutByte(XIRCREG2_GPR2, 0x04|0); /* drive MDCK low */ in mii_idle()
358 PutByte(XIRCREG2_GPR2, 0x04|1); /* and drive MDCK high */ in mii_idle()
370 PutByte(XIRCREG2_GPR2, 0x0c|2|0); /* set MDIO */ in mii_putbit()
372 PutByte(XIRCREG2_GPR2, 0x0c|2|1); /* and drive MDCK high */ in mii_putbit()
375 PutByte(XIRCREG2_GPR2, 0x0c|0|0); /* clear MDIO */ in mii_putbit()
377 PutByte(XIRCREG2_GPR2, 0x0c|0|1); /* and drive MDCK high */ in mii_putbit()
382 PutWord(XIRCREG2_GPR2-1, 0x0e0e); in mii_putbit()
384 PutWord(XIRCREG2_GPR2-1, 0x0f0f); in mii_putbit()
387 PutWord(XIRCREG2_GPR2-1, 0x0c0c); in mii_putbit()
389 PutWord(XIRCREG2_GPR2-1, 0x0d0d); in mii_putbit()
403 PutByte(XIRCREG2_GPR2, 4|0); /* drive MDCK low */ in mii_getbit()
408 return d & 0x20; /* read MDIO */ in mii_getbit()
423 unsigned data=0, m; in mii_rd()
426 for (i=0; i < 32; i++) /* 32 bit preamble */ in mii_rd()
428 mii_wbits(ioaddr, 0x06, 4); /* Start and opcode for read */ in mii_rd()
448 for (i=0; i < 32; i++) /* 32 bit preamble */ in mii_wr()
450 mii_wbits(ioaddr, 0x05, 4); /* Start and opcode for write */ in mii_wr()
454 mii_putbit(ioaddr, 0); in mii_wr()
522 * Detect the type of the card. s is the buffer with the data of tuple 0x20
523 * Returns: 0 := not supported
526 * Ethernet 0x01
527 * Tokenring 0x02
528 * Arcnet 0x04
529 * Wireless 0x08
530 * Modem 0x10
531 * GSM only 0x20
533 * Pocket 0x10
534 * External 0x20
535 * Creditcard 0x40
536 * Cardbus 0x80
551 return 0; in set_card_type()
561 local->mohawk = 0; in set_card_type()
562 local->dingo = 0; in set_card_type()
563 local->modem = 0; in set_card_type()
565 if (!(prodid & 0x40)) { in set_card_type()
567 return 0; in set_card_type()
569 if (!(mediaid & 0x01)) { in set_card_type()
571 return 0; in set_card_type()
573 if (mediaid & 0x10) { in set_card_type()
602 return 0; in set_card_type()
620 return 0; in has_ce2_string()
628 if ((p_dev->resource[0]->start & 0xf) == 8) in xirc2ps_config_modem()
631 p_dev->resource[0]->end = 16; in xirc2ps_config_modem()
633 p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH; in xirc2ps_config_modem()
634 p_dev->resource[0]->flags |= IO_DATA_PATH_WIDTH_16; in xirc2ps_config_modem()
639 p_dev->resource[1]->start = p_dev->resource[0]->start; in xirc2ps_config_modem()
640 for (ioaddr = 0x300; ioaddr < 0x400; ioaddr += 0x10) { in xirc2ps_config_modem()
641 p_dev->resource[0]->start = ioaddr; in xirc2ps_config_modem()
643 return 0; in xirc2ps_config_modem()
654 tmp += (*pass ? (p_dev->config_index & 0x20 ? -24 : 8) in xirc2ps_config_check()
655 : (p_dev->config_index & 0x20 ? 8 : -24)); in xirc2ps_config_check()
657 if ((p_dev->resource[0]->start & 0xf) == 8) in xirc2ps_config_check()
660 p_dev->resource[0]->end = 18; in xirc2ps_config_check()
662 p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH; in xirc2ps_config_check()
663 p_dev->resource[0]->flags |= IO_DATA_PATH_WIDTH_16; in xirc2ps_config_check()
668 p_dev->resource[1]->start = p_dev->resource[0]->start; in xirc2ps_config_check()
669 p_dev->resource[0]->start = tmp; in xirc2ps_config_check()
682 if ((tuple->TupleData[0] != 2) || (tuple->TupleData[1] != 1) || in pcmcia_get_mac_ce()
687 return 0; in pcmcia_get_mac_ce()
706 if (link->has_manf_id == 0) { in xirc2ps_config()
729 pr_notice("Unknown Card Manufacturer ID: 0x%04x\n", in xirc2ps_config()
743 /* not found: try to get the node-id from tuple 0x89 */ in xirc2ps_config()
745 len = pcmcia_get_tuple(link, 0x89, &buf); in xirc2ps_config()
746 /* data layout looks like tuple 0x22 */ in xirc2ps_config()
779 for (pass=0; pass < 2; pass++) in xirc2ps_config()
790 link->resource[0]->end = 16; in xirc2ps_config()
791 link->resource[0]->flags |= IO_DATA_PATH_WIDTH_16; in xirc2ps_config()
792 for (ioaddr = 0x300; ioaddr < 0x400; ioaddr += 0x10) { in xirc2ps_config()
793 link->resource[0]->start = ioaddr; in xirc2ps_config()
797 link->resource[0]->start = 0; /* let CS decide */ in xirc2ps_config()
824 link->resource[1]->start & 0xff); in xirc2ps_config()
829 (link->resource[1]->start >> 8) & 0xff); in xirc2ps_config()
834 * is at 0x0800. So we allocate a window into the attribute in xirc2ps_config()
839 link->resource[2]->start = link->resource[2]->end = 0; in xirc2ps_config()
840 if ((err = pcmcia_request_window(link, link->resource[2], 0))) in xirc2ps_config()
843 local->dingo_ccr = ioremap(link->resource[2]->start, 0x1000) + 0x0800; in xirc2ps_config()
844 if ((err = pcmcia_map_mem_page(link, link->resource[2], 0))) in xirc2ps_config()
850 writeb(0x47, local->dingo_ccr + CISREG_COR); in xirc2ps_config()
851 ioaddr = link->resource[0]->start; in xirc2ps_config()
852 writeb(ioaddr & 0xff , local->dingo_ccr + CISREG_IOBASE_0); in xirc2ps_config()
853 writeb((ioaddr >> 8)&0xff , local->dingo_ccr + CISREG_IOBASE_1); in xirc2ps_config()
855 #if 0 in xirc2ps_config()
859 for (i=0; i < 7; i++) { in xirc2ps_config()
865 for (i=0; i < 4; i++) { in xirc2ps_config()
866 tmp = readb(local->dingo_ccr + 0x20 + i*2); in xirc2ps_config()
871 for (i=0; i < 10; i++) { in xirc2ps_config()
872 tmp = readb(local->dingo_ccr + 0x40 + i*2); in xirc2ps_config()
879 writeb(0x01, local->dingo_ccr + 0x20); in xirc2ps_config()
880 writeb(0x0c, local->dingo_ccr + 0x22); in xirc2ps_config()
881 writeb(0x00, local->dingo_ccr + 0x24); in xirc2ps_config()
882 writeb(0x00, local->dingo_ccr + 0x26); in xirc2ps_config()
883 writeb(0x00, local->dingo_ccr + 0x28); in xirc2ps_config()
887 local->probe_port=0; in xirc2ps_config()
898 dev->base_addr = link->resource[0]->start; in xirc2ps_config()
915 return 0; in xirc2ps_config()
934 iounmap(local->dingo_ccr - 0x0800); in xirc2ps_release()
951 return 0; in xirc2ps_suspend()
963 return 0; in xirc2ps_resume()
992 PutByte(XIRCREG_CR, 0); in xirc2ps_interrupt()
1002 bytes_rcvd = 0; in xirc2ps_interrupt()
1004 if (int_status == 0xff) { /* card may be ejected */ in xirc2ps_interrupt()
1010 SelectPage(0x40); in xirc2ps_interrupt()
1012 PutByte(XIRCREG40_RXST0, (~rx_status & 0xff)); in xirc2ps_interrupt()
1015 PutByte(XIRCREG40_TXST0, 0); in xirc2ps_interrupt()
1016 PutByte(XIRCREG40_TXST1, 0); in xirc2ps_interrupt()
1022 SelectPage(0); in xirc2ps_interrupt()
1044 if (lp->silicon == 0 ) { /* work around a hardware bug */ in xirc2ps_interrupt()
1049 SelectPage(0); in xirc2ps_interrupt()
1051 if (rhsa >= 0x8000) in xirc2ps_interrupt()
1052 rhsa = 0; in xirc2ps_interrupt()
1053 if (rhsa + pktlen > 0x8000) { in xirc2ps_interrupt()
1056 for (i=0; i < pktlen ; i++, rhsa++) { in xirc2ps_interrupt()
1058 if (rhsa == 0x8000) { in xirc2ps_interrupt()
1059 rhsa = 0; in xirc2ps_interrupt()
1068 #if 0 in xirc2ps_interrupt()
1082 for (i=0; i < len ; i += 4, p++) { in xirc2ps_interrupt()
1084 __asm__("rorl $16,%0\n\t" in xirc2ps_interrupt()
1086 : "0" (a)); in xirc2ps_interrupt()
1119 PutWord(XIRCREG0_DO, 0x8000); /* issue cmd: skip_rx_packet */ in xirc2ps_interrupt()
1124 if (rx_status & 0x10) { /* Receive overrun */ in xirc2ps_interrupt()
1145 if (tx_status & 0x0002) { /* Excessive collisions */ in xirc2ps_interrupt()
1149 if (tx_status & 0x0040) in xirc2ps_interrupt()
1178 if (int_status != 0xff && (int_status = GetByte(XIRCREG_ISR)) != 0) in xirc2ps_interrupt()
1241 SelectPage(0); in do_start_xmit()
1243 freespace = GetWord(XIRCREG0_TSO) & 0x7fff; in do_start_xmit()
1278 for (i = 0; i < 6; i++) { in set_address()
1309 sa_info.page_nr = 0x50 - 1; in set_addresses()
1314 i = 0; in set_addresses()
1322 SelectPage(0); in set_addresses()
1337 SelectPage(0x42); in set_multicast_list()
1338 value = GetByte(XIRCREG42_SWC1) & 0xC0; in set_multicast_list()
1341 PutByte(XIRCREG42_SWC1, value | 0x06); /* set MPE and PME */ in set_multicast_list()
1343 PutByte(XIRCREG42_SWC1, value | 0x02); /* set MPE */ in set_multicast_list()
1346 PutByte(XIRCREG42_SWC1, value | 0x01); in set_multicast_list()
1347 SelectPage(0x40); in set_multicast_list()
1350 SelectPage(0x40); in set_multicast_list()
1353 PutByte(XIRCREG42_SWC1, value | 0x00); in set_multicast_list()
1355 SelectPage(0); in set_multicast_list()
1371 local->probe_port = 0; in do_config()
1377 return 0; in do_config()
1402 return 0; in do_open()
1409 snprintf(info->bus_info, sizeof(info->bus_info), "PCMCIA 0x%lx", in netdev_get_drvinfo()
1433 data->phy_id = 0; /* we have only this address */ in do_ioctl()
1436 data->val_out = mii_rd(ioaddr, data->phy_id & 0x1f, in do_ioctl()
1437 data->reg_num & 0x1f); in do_ioctl()
1440 mii_wr(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in, in do_ioctl()
1446 return 0; in do_ioctl()
1457 PutByte(XIRCREG4_GPR1, 0); /* clear bit 0: power down */ in hardreset()
1460 PutByte(XIRCREG4_GPR1, 1); /* set bit 0: power up */ in hardreset()
1462 PutByte(XIRCREG4_GPR1, 1 | 4); /* set bit 0: power up, bit 2: AIC */ in hardreset()
1478 PutByte(XIRCREG_CR, 0); /* clear */ in do_reset()
1482 /* set pin GP1 and GP2 to output (0x0c) in do_reset()
1483 * set GP1 to low to power up the ML6692 (0x00) in do_reset()
1484 * set GP2 to high to power up the 10Mhz chip (0x02) in do_reset()
1486 PutByte(XIRCREG4_GPR0, 0x0e); in do_reset()
1492 local->last_ptr_value = 0; in do_reset()
1493 local->silicon = local->mohawk ? (GetByte(XIRCREG4_BOV) & 0x70) >> 4 in do_reset()
1494 : (GetByte(XIRCREG4_BOV) & 0x30) >> 4; in do_reset()
1500 local->probe_port = 0; in do_reset()
1503 SelectPage(0x42); in do_reset()
1504 PutByte(XIRCREG42_SWC1, 0xC0); in do_reset()
1506 SelectPage(0x42); in do_reset()
1507 PutByte(XIRCREG42_SWC1, 0x80); in do_reset()
1511 #if 0 in do_reset()
1513 SelectPage(0); in do_reset()
1521 PutByte(XIRCREG1_IMR0, 0xff); /* allow all ints */ in do_reset()
1524 #if 0 in do_reset()
1531 SelectPage(0x42); in do_reset()
1532 PutByte(XIRCREG42_SWC0, 0x20); /* disable source insertion */ in do_reset()
1537 * settable with the scipper version 2 which is revision 0. in do_reset()
1541 PutWord(XIRCREG2_RBS, 0x2000); in do_reset()
1549 * to move the offset pointer back to 0. in do_reset()
1551 SelectPage(0); in do_reset()
1552 PutWord(XIRCREG0_DO, 0x2000); /* change offset command, off=0 */ in do_reset()
1555 SelectPage(0x40); /* Bit 7 ... bit 0 */ in do_reset()
1556 PutByte(XIRCREG40_RMASK0, 0xff); /* ROK, RAB, rsv, RO, CRC, AE, PTL, MP */ in do_reset()
1557 PutByte(XIRCREG40_TMASK0, 0xff); /* TOK, TAB, SQE, LL, TU, JAB, EXC, CRS */ in do_reset()
1558 PutByte(XIRCREG40_TMASK1, 0xb0); /* rsv, rsv, PTD, EXT, rsv,rsv,rsv, rsv*/ in do_reset()
1559 PutByte(XIRCREG40_RXST0, 0x00); /* ROK, RAB, REN, RO, CRC, AE, PTL, MP */ in do_reset()
1560 PutByte(XIRCREG40_TXST0, 0x00); /* TOK, TAB, SQE, LL, TU, JAB, EXC, CRS */ in do_reset()
1561 PutByte(XIRCREG40_TXST1, 0x00); /* TEN, rsv, PTD, EXT, retry_counter:4 */ in do_reset()
1567 PutByte(XIRCREG2_MSR, GetByte(XIRCREG2_MSR) | 0x08); in do_reset()
1571 SelectPage(0x42); in do_reset()
1573 PutByte(XIRCREG42_SWC1, 0xC0); in do_reset()
1575 PutByte(XIRCREG42_SWC1, 0x80); in do_reset()
1581 SelectPage(0); in do_reset()
1589 PutByte(XIRCREG2_LED, 0x3b); in do_reset()
1591 PutByte(XIRCREG2_LED, 0x3a); in do_reset()
1594 PutByte(0x0b, 0x04); /* 100 Mbit LED */ in do_reset()
1599 SelectPage(0x40); in do_reset()
1605 PutByte(XIRCREG1_IMR0, 0xff); in do_reset()
1607 SelectPage(0); in do_reset()
1610 if (!(GetByte(0x10) & 0x01)) in do_reset()
1611 PutByte(0x10, 0x11); /* unmask master-int bit */ in do_reset()
1617 /* We should switch back to page 0 to avoid a bug in revision 0 in do_reset()
1620 SelectPage(0); in do_reset()
1637 local->probe_port = 0; in init_mii()
1641 status = mii_rd(ioaddr, 0, 1); in init_mii()
1642 if ((status & 0xff00) != 0x7800) in init_mii()
1643 return 0; /* No MII */ in init_mii()
1645 local->new_mii = (mii_rd(ioaddr, 0, 2) != 0xffff); in init_mii()
1648 control = 0x1000; /* auto neg */ in init_mii()
1650 control = 0x2000; /* no auto neg, 100mbs mode */ in init_mii()
1652 control = 0x0000; /* no auto neg, 10mbs mode */ in init_mii()
1653 mii_wr(ioaddr, 0, 0, control, 16); in init_mii()
1655 control = mii_rd(ioaddr, 0, 0); in init_mii()
1657 if (control & 0x0400) { in init_mii()
1659 local->probe_port = 0; in init_mii()
1660 return 0; in init_mii()
1668 for (i=0; i < 35; i++) { in init_mii()
1670 status = mii_rd(ioaddr, 0, 1); in init_mii()
1671 if ((status & 0x0020) && (status & 0x0004)) in init_mii()
1675 if (!(status & 0x0020)) { in init_mii()
1678 control = 0x0000; in init_mii()
1679 mii_wr(ioaddr, 0, 0, control, 16); in init_mii()
1681 SelectPage(0); in init_mii()
1685 linkpartner = mii_rd(ioaddr, 0, 5); in init_mii()
1687 if (linkpartner & 0x0080) { in init_mii()
1706 PutByte(XIRCREG4_GPR1, 0); /* clear bit 0: power down */ in do_powerdown()
1707 SelectPage(0); in do_powerdown()
1724 SelectPage(0); in do_stop()
1725 PutByte(XIRCREG_CR, 0); /* disable interrupts */ in do_stop()
1726 SelectPage(0x01); in do_stop()
1727 PutByte(XIRCREG1_IMR0, 0x00); /* forbid all ints */ in do_stop()
1729 PutByte(XIRCREG4_GPR1, 0); /* clear bit 0: power down */ in do_stop()
1730 SelectPage(0); in do_stop()
1733 return 0; in do_stop()
1737 PCMCIA_PFC_DEVICE_MANF_CARD(0, 0x0089, 0x110a),
1738 PCMCIA_PFC_DEVICE_MANF_CARD(0, 0x0138, 0x110a),
1739 PCMCIA_PFC_DEVICE_PROD_ID13(0, "Xircom", "CEM28", 0x2e3ee845, 0x0ea978ea),
1740 PCMCIA_PFC_DEVICE_PROD_ID13(0, "Xircom", "CEM33", 0x2e3ee845, 0x80609023),
1741 PCMCIA_PFC_DEVICE_PROD_ID13(0, "Xircom", "CEM56", 0x2e3ee845, 0xa650c32a),
1742 PCMCIA_PFC_DEVICE_PROD_ID13(0, "Xircom", "REM10", 0x2e3ee845, 0x76df1d29),
1743 PCMCIA_PFC_DEVICE_PROD_ID13(0, "Xircom", "XEM5600", 0x2e3ee845, 0xf1403719),
1744 PCMCIA_PFC_DEVICE_PROD_ID12(0, "Xircom", "CreditCard Ethernet+Modem II", 0x2e3ee845, 0xeca401bf),
1745 PCMCIA_DEVICE_MANF_CARD(0x01bf, 0x010a),
1746 PCMCIA_DEVICE_PROD_ID13("Toshiba Information Systems", "TPCENET", 0x1b3b94fe, 0xf381c1a2),
1747 PCMCIA_DEVICE_PROD_ID13("Xircom", "CE3-10/100", 0x2e3ee845, 0x0ec0ac37),
1748 PCMCIA_DEVICE_PROD_ID13("Xircom", "PS-CE2-10", 0x2e3ee845, 0x947d9073),
1749 PCMCIA_DEVICE_PROD_ID13("Xircom", "R2E-100BTX", 0x2e3ee845, 0x2464a6e3),
1750 PCMCIA_DEVICE_PROD_ID13("Xircom", "RE-10", 0x2e3ee845, 0x3e08d609),
1751 PCMCIA_DEVICE_PROD_ID13("Xircom", "XE2000", 0x2e3ee845, 0xf7188e46),
1752 PCMCIA_DEVICE_PROD_ID12("Compaq", "Ethernet LAN Card", 0x54f7c49c, 0x9fd2f0a2),
1753 PCMCIA_DEVICE_PROD_ID12("Compaq", "Netelligent 10/100 PC Card", 0x54f7c49c, 0xefe96769),
1754 …CE_PROD_ID12("Intel", "EtherExpress(TM) PRO/100 PC Card Mobile Adapter16", 0x816cc815, 0x174397db),
1755 PCMCIA_DEVICE_PROD_ID12("Toshiba", "10/100 Ethernet PC Card", 0x44a09d9c, 0xb44deecf),
1757 /* PCMCIA_DEVICE_MANF_CARD(0x0105, 0x010a), */
1783 #define MAYBE_SET(X,Y) if (ints[0] >= Y && ints[Y] != -1) { X = ints[Y]; } in setup_xirc2ps_cs()