Lines Matching +full:tx +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
34 /* Jumbo frame support for Tx & Rx. Default: disabled (cleared) */
37 /* VLAN Rx & Tx frame support. Default: disabled (cleared) */
40 /* Enable recognition of flow control frames on Rx. Default: enabled (set) */
53 /* Enable Length/Type error checking for incoming frames. When this option is
61 /* Enable the transmitter. Default: enabled (set) */
64 /* Enable the receiver. Default: enabled (set) */
108 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
109 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
126 /* Default TX/RX Threshold and delay timer values for SGDMA mode */
132 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
133 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
150 #define XAE_TPF_OFFSET 0x00000004 /* Tx Pause Frame */
151 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
154 #define XAE_IE_OFFSET 0x00000014 /* Interrupt enable */
155 #define XAE_TTAG_OFFSET 0x00000018 /* Tx VLAN TAG */
165 #define XAE_TC_OFFSET 0x00000408 /* Tx Configuration */
178 #define XAE_FFE_OFFSET 0x0000070C /* Frame Filter Enable */
181 #define XAE_AM0_OFFSET 0x00000750 /* Frame Filter Mask Value Bytes 3-0 */
182 #define XAE_AM1_OFFSET 0x00000754 /* Frame Filter Mask Value Bytes 7-4 */
184 #define XAE_TX_VLAN_DATA_OFFSET 0x00004000 /* TX VLAN data table address */
193 #define XAE_RAF_TXVTAGMODE_MASK 0x00000018 /* Tx VLAN TAG mode */
195 #define XAE_RAF_TXVSTRPMODE_MASK 0x00000180 /* Tx VLAN STRIP mode */
201 #define XAE_RAF_RXBADFRMEN_MASK 0x00004000 /* Recv Bad Frame Enable */
202 #define XAE_RAF_TXVTAGMODE_SHIFT 3 /* Tx Tag mode shift bits */
204 #define XAE_RAF_TXVSTRPMODE_SHIFT 7 /* Tx strip mode shift bits*/
208 #define XAE_TPF_TPFV_MASK 0x0000FFFF /* Tx pause frame value */
209 /* Transmit inter-frame gap adjustment value */
222 #define XAE_INT_TXCMPIT_MASK 0x00000020 /* Tx complete */
242 #define XAE_RCW1_JUM_MASK 0x40000000 /* Jumbo frame enable */
243 /* In-Band FCS enable (FCS not stripped) */
245 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
246 #define XAE_RCW1_VLAN_MASK 0x08000000 /* VLAN frame enable */
258 #define XAE_TC_JUM_MASK 0x40000000 /* Jumbo frame enable */
259 /* In-Band FCS enable (FCS not generated) */
261 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
262 #define XAE_TC_VLAN_MASK 0x08000000 /* VLAN frame enable */
263 /* Inter-frame gap adjustment enable */
267 #define XAE_FCC_FCRX_MASK 0x20000000 /* Rx flow control enable */
268 #define XAE_FCC_FCTX_MASK 0x40000000 /* Tx flow control enable */
272 #define XAE_EMMC_RGMII_MASK 0x20000000 /* RGMII mode enable */
273 #define XAE_EMMC_SGMII_MASK 0x10000000 /* SGMII mode enable */
274 #define XAE_EMMC_GPCS_MASK 0x08000000 /* 1000BaseX mode enable */
275 #define XAE_EMMC_HOST_MASK 0x04000000 /* Host interface enable */
276 #define XAE_EMMC_TX16BIT 0x02000000 /* 16 bit Tx client enable */
277 #define XAE_EMMC_RX16BIT 0x01000000 /* 16 bit Rx client enable */
285 #define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */
305 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable */
330 #define XAE_FMI_PM_MASK 0x80000000 /* Promis. mode enable */
366 /* enum temac_stat - TEMAC statistics counters
422 * struct axidma_bd - Axi Dma buffer descriptor layout
448 u32 app1; /* TX start << 16 | insert */
449 u32 app2; /* TX csum seed */
458 * struct skbuf_dma_descriptor - skb for each dma descriptor
474 * struct axienet_local - axienet private per device data
482 * @axi_clk: AXI4-Lite bus clock
483 * @misc_clks: Misc ethernet clocks (AXI4-Stream, Ref, MGT clocks)
499 * @napi_tx: NAPI TX control structure
500 * @tx_dma_cr: Nominal content of TX DMA control register
501 * @tx_bd_v: Virtual address of the TX buffer descriptor ring
502 * @tx_bd_p: Physical address(start address) of the TX buffer descr. ring
503 * @tx_bd_num: Size of TX buffer descriptor ring
504 * @tx_bd_ci: Stores the next Tx buffer descriptor in the ring that may be
505 * complete. Only updated at runtime by TX NAPI poll.
506 * @tx_bd_tail: Stores the index of the next Tx buffer descriptor in the ring
508 * @tx_packets: TX packet count for statistics
509 * @tx_bytes: TX byte count for statistics
510 * @tx_stat_sync: Synchronization object for TX stats
513 * @hw_last_counter: Last-seen value of each statistic counter
524 * @tx_irq: Axidma TX IRQ number
527 * @phy_mode: Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
537 * @coalesce_count_tx: Store the irq coalesce on TX side.
538 * @coalesce_usec_tx: IRQ coalesce delay for TX
540 * @tx_chan: TX DMA channel.
542 * @tx_skb_ring: Pointer to TX skb ring buffer array.
544 * @tx_ring_head: TX skb ring buffer head index.
545 * @tx_ring_tail: TX skb ring buffer tail index.
629 * struct axienet_option - Used to set axi ethernet hardware options
641 * axienet_ior - Memory mapped Axi Ethernet register read
651 return ioread32(lp->regs + offset); in axienet_ior()
661 if (lp->mii_bus) in axienet_lock_mii()
662 mutex_lock(&lp->mii_bus->mdio_lock); in axienet_lock_mii()
667 if (lp->mii_bus) in axienet_unlock_mii()
668 mutex_unlock(&lp->mii_bus->mdio_lock); in axienet_unlock_mii()
672 * axienet_iow - Memory mapped Axi Ethernet register write
683 iowrite32(value, lp->regs + offset); in axienet_iow()
687 * axienet_dma_out32 - Memory mapped Axi DMA register write.
699 iowrite32(value, lp->dma_regs + reg); in axienet_dma_out32()
704 * axienet_dma_out64 - Memory mapped Axi DMA register write.
715 iowrite64(value, lp->dma_regs + reg); in axienet_dma_out64()
721 if (lp->features & XAE_FEATURE_DMA_64BIT) in axienet_dma_out_addr()