Lines Matching +full:rx +full:- +full:pcs
1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
34 /* Jumbo frame support for Tx & Rx. Default: disabled (cleared) */
37 /* VLAN Rx & Tx frame support. Default: disabled (cleared) */
40 /* Enable recognition of flow control frames on Rx. Default: enabled (set) */
126 /* Default TX/RX Threshold and delay timer values for SGDMA mode */
142 #define XAXIDMA_BD_STS_RXSOF_MASK 0x08000000 /* First rx pkt */
143 #define XAXIDMA_BD_STS_RXEOF_MASK 0x04000000 /* Last rx pkt */
151 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
156 #define XAE_RTAG_OFFSET 0x0000001C /* Rx VLAN TAG */
161 #define XAE_PPST_OFFSET 0x00000030 /* PCS PMA Soft Temac Status Reg */
163 #define XAE_RCW0_OFFSET 0x00000400 /* Rx Configuration Word 0 */
164 #define XAE_RCW1_OFFSET 0x00000404 /* Rx Configuration Word 1 */
168 #define XAE_PHYC_OFFSET 0x00000414 /* RX Max Frame Configuration */
181 #define XAE_AM0_OFFSET 0x00000750 /* Frame Filter Mask Value Bytes 3-0 */
182 #define XAE_AM1_OFFSET 0x00000754 /* Frame Filter Mask Value Bytes 7-4 */
185 #define XAE_RX_VLAN_DATA_OFFSET 0x00008000 /* RX VLAN data table address */
194 #define XAE_RAF_RXVTAGMODE_MASK 0x00000060 /* Rx VLAN TAG mode */
196 #define XAE_RAF_RXVSTRPMODE_MASK 0x00000600 /* Rx VLAN STRIP mode */
203 #define XAE_RAF_RXVTAGMODE_SHIFT 5 /* Rx Tag mode shift bits */
205 #define XAE_RAF_RXVSTRPMODE_SHIFT 9 /* Rx Strip mode shift bits*/
209 /* Transmit inter-frame gap adjustment value */
219 #define XAE_INT_RXCMPIT_MASK 0x00000004 /* Rx complete */
220 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
221 #define XAE_INT_RXFIFOOVR_MASK 0x00000010 /* Rx fifo overrun */
223 #define XAE_INT_RXDCMLOCK_MASK 0x00000040 /* Rx Dcm Lock */
243 /* In-Band FCS enable (FCS not stripped) */
259 /* In-Band FCS enable (FCS not generated) */
263 /* Inter-frame gap adjustment enable */
267 #define XAE_FCC_FCRX_MASK 0x20000000 /* Rx flow control enable */
277 #define XAE_EMMC_RX16BIT 0x01000000 /* 16 bit Rx client enable */
285 #define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */
362 /* Xilinx PCS/PMA PHY register for switching 1000BaseX or SGMII */
366 /* enum temac_stat - TEMAC statistics counters
422 * struct axidma_bd - Axi Dma buffer descriptor layout
458 * struct skbuf_dma_descriptor - skb for each dma descriptor
474 * struct axienet_local - axienet private per device data
479 * @pcs_phy: Reference to PCS/PMA PHY if used
480 * @pcs: phylink pcs structure for PCS PHY
482 * @axi_clk: AXI4-Lite bus clock
483 * @misc_clks: Misc ethernet clocks (AXI4-Stream, Ref, MGT clocks)
489 * @napi_rx: NAPI RX control structure
490 * @rx_dma_cr: Nominal content of RX DMA control register
491 * @rx_bd_v: Virtual address of the RX buffer descriptor ring
492 * @rx_bd_p: Physical address(start address) of the RX buffer descr. ring
493 * @rx_bd_num: Size of RX buffer descriptor ring
494 * @rx_bd_ci: Stores the index of the Rx buffer descriptor in the ring being
496 * @rx_packets: RX packet count for statistics
497 * @rx_bytes: RX byte count for statistics
498 * @rx_stat_sync: Synchronization object for RX stats
513 * @hw_last_counter: Last-seen value of each statistic counter
525 * @rx_irq: Axidma RX IRQ number
527 * @phy_mode: Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
534 * @rxmem: Stores rx memory size for jumbo frame handling.
535 * @coalesce_count_rx: Store the irq coalesce on RX side.
536 * @coalesce_usec_rx: IRQ coalesce delay for RX
541 * @rx_chan: RX DMA channel.
543 * @rx_skb_ring: Pointer to RX skb ring buffer array.
546 * @rx_ring_head: RX skb ring buffer head index.
547 * @rx_ring_tail: RX skb ring buffer tail index.
557 struct phylink_pcs pcs; member
629 * struct axienet_option - Used to set axi ethernet hardware options
641 * axienet_ior - Memory mapped Axi Ethernet register read
651 return ioread32(lp->regs + offset); in axienet_ior()
661 if (lp->mii_bus) in axienet_lock_mii()
662 mutex_lock(&lp->mii_bus->mdio_lock); in axienet_lock_mii()
667 if (lp->mii_bus) in axienet_unlock_mii()
668 mutex_unlock(&lp->mii_bus->mdio_lock); in axienet_unlock_mii()
672 * axienet_iow - Memory mapped Axi Ethernet register write
683 iowrite32(value, lp->regs + offset); in axienet_iow()
687 * axienet_dma_out32 - Memory mapped Axi DMA register write.
699 iowrite32(value, lp->dma_regs + reg); in axienet_dma_out32()
704 * axienet_dma_out64 - Memory mapped Axi DMA register write.
715 iowrite64(value, lp->dma_regs + reg); in axienet_dma_out64()
721 if (lp->features & XAE_FEATURE_DMA_64BIT) in axienet_dma_out_addr()